Replicated Logic Debugging for Intermittent IC Errors
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Solution Overview
Problem
Complex integrated circuit designs, such as ASICs, are difficult to verify and debug due to their size and complexity, with traditional simulation tools being inadequate for identifying and reconstructing intermittent errors.
Innovation Solution
A method and system using replicated logic are employed, where a portion of the circuit is replicated, and trigger logic, clock control logic, and delay logic are inserted to analyze errors by pausing and stepping through the replicated logic, allowing for detailed examination of problem areas and verification of circuit functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional simulation tools are used to verify complex IC designs, then the verification process becomes increasingly difficult and ineffective, but using replicated logic with trigger and delay elements enables effective error reproduction and analysis
Solution Approach 1:
The patent creates a replicated version of the circuit under test, including replicated logic elements and replicated delay elements. This copy allows observers to monitor internal signals without interfering with the normal operation of the original circuit, enabling effective error reproduction and analysis while maintaining the original design's functionality.
Solution Approach 2:
The verification system is segmented into distinct functional components: the original circuit, replicated logic elements, replicated delay elements, and trigger elements. This segmentation allows each component to perform its specific function independently, making the overall complex verification process manageable and effective.
2Measurement precision
If intermittent errors occur in the circuit, then traditional logic analyzers cannot effectively capture and reconstruct the errors, but replicated logic with trigger elements enables capturing the exact sequence of inputs leading to errors
Solution Approach 1:
The trigger elements are pre-configured with trigger conditions that monitor specific signal patterns in the replicated logic. When these predetermined conditions are met, the trigger elements automatically capture and hold the relevant signal states, enabling precise error capture without requiring manual intervention or post-processing of large amounts of data.
Solution Approach 2:
The replicated delay elements act as intermediaries between the original circuit signals and the observation points. These delay elements reproduce the timing characteristics of the original circuit, allowing observers to capture and analyze the exact sequence of events leading to intermittent errors while maintaining temporal accuracy.
3Ease of operation
If the original circuit is modified for debugging purposes, then the circuit functionality may be altered, but using replicated logic allows debugging without affecting the original circuit operation
Solution Approach 1:
Instead of modifying the original circuit, the patent creates a complete replicated version of the circuit logic and delay elements. This copy can be freely instrumented with trigger elements and observation points for debugging purposes, while the original circuit remains untouched and maintains its intended functionality and performance characteristics.
Data Source
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AI summary
A method and system for debug and test using replicated logic is described. A representation of a circuit is compiled. The circuit includes a replicated portion and delay logic to delay inputs into the replicated portion. The circuit may also include trigger logic and clock control logic to enable execution of the replicated portion of the circuit to be paused when a trigger condition occurs. The compiled representation of the circuit may be programmed into a hardware device. A debugger may then be invoked. One or more triggering signals are selected. For each selected triggering signal, one or more states are selected to setup a trigger condition. The hardware device may then be run. The replicated portion of the circuit will be paused when the trigger condition occurs. The states of registers in the replicated portion of the circuit and the sequence of inputs that led to the trigger condition are recorded. This recorded data may then used to generate a test to be run on a software simulator when the circuit is modified.