Re-programmable BIST for SoC Test Coverage
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Solution Overview
Problem
Existing self-test solutions for digital systems, particularly in Systems on a Chip (SoC), face limitations in test coverage and diagnostic resolution due to their fixed nature and reliance on software-based approaches, which are often lengthy, costly, and inefficient.
Innovation Solution
The integration of a one-time programmable eFuse for seed data input into a Pseudo Random Pattern Generator (PRPG) and the use of a Multiple Input Shift Register (MISR) for signature output comparison enhances the self-test capability by increasing coverage through re-programmability in built-in self-test (BIST) hardware modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-based self-test is used, then system-level testing can be implemented, but diagnostic resolution is poor and testing is lengthy and expensive
Solution Approach 1:
The patent introduces BIST hardware modules as intermediary components between the digital circuit and test equipment. These modules include a pattern generator that creates test patterns, a circuit under test, and a response analyzer that captures and analyzes test responses. This intermediary hardware layer enables precise diagnostic resolution by directly testing circuit components rather than relying on software-level observations.
Solution Approach 2:
The patent replaces software-based testing mechanisms with hardware-based BIST mechanisms. Instead of using software to control and analyze tests at the system level, the invention implements dedicated hardware modules (pattern generator, response analyzer) that operate at the circuit level, providing faster and more precise testing similar to how mechanical systems are replaced with automated control systems.
2Ease of manufacture
If fixed BIST architecture is used, then basic self-test functionality is achieved, but test coverage is limited
Solution Approach 1:
The patent implements re-programmability in the BIST hardware modules, allowing the test patterns and response analysis parameters to be dynamically configured after manufacture. The pattern generator can be re-programmed with different test patterns, and the response analyzer can be re-programmed with different expected responses, enabling the same hardware to adapt to different testing scenarios and increase test coverage without requiring additional hardware.
Solution Approach 2:
The patent enables changes in test parameters through re-programming the BIST modules. By modifying the seed values for pattern generation, changing the test pattern sequences, and adjusting the expected response signatures, the system can achieve different levels of test coverage. This parameter flexibility allows the fixed hardware architecture to achieve variable test coverage suitable for different application requirements.
3Adaptability or versatility
If re-programmable BIST is implemented, then test coverage is increased, but hardware complexity increases
Solution Approach 1:
The patent designs the BIST hardware modules to serve multiple functions. The pattern generator can generate various test patterns through re-programming, the same module can serve different circuit blocks, and the response analyzer can analyze different types of responses. This multi-functionality reduces the need for separate dedicated test hardware for each circuit block, thereby increasing test coverage without proportionally increasing overall hardware complexity.
Data Source
AI summary
A built-in self-test (BIST) method includes providing expanded test patterns to a logic circuit under test, generating a first signature based on a response of the logic circuit to the expanded test patterns, generating a second signature based on the first signature, wherein the second signature is a compressed version of the first signature, selecting one of the first signature or the second signature in response to a control signal, comparing the selected one of the first signature or the second signature to an expected signature, and, based on the comparison of the selected one of the first signature or the second signature to the expected signature, determining that the logic circuit passes or fails BIST.