Reprogrammable DSP With Subordinate FPGA Fabric
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Solution Overview
Problem
Current DSP solutions lack the ability to reconfigure their instruction sets post-manufacturing, limiting adaptability to real-world phenomena and increasing silicon area consumption, while existing reprogrammable array DSPs operate independently of software programmable architectures, complicating design flows and increasing costs.
Innovation Solution
A software programmable DSP with a field-programmable instruction set that allows for reconfiguration post-delivery, where the FPGA fabric is subordinate to the DSP, enabling synchronous operation and easy conversion to ASICs, and providing a method for optimizing instruction sets and migrating designs to smaller dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a software programmable DSP uses fixed instruction sets manufactured in silicon, then manufacturing cost is reduced and production is simplified, but the ability to adapt to real-world phenomena and customize instructions is lost
Solution Approach 1:
The patent implements a field-reprogrammable instruction set that allows the DSP to dynamically change its instruction set after manufacturing. The instruction set can be reconfigured in the field to adapt to different real-world applications and phenomena, resolving the contradiction between fixed manufacturing simplicity and post-manufacturing adaptability.
Solution Approach 2:
The patent enables changing the parameters of the instruction set itself after manufacturing by providing mechanisms to load and execute different instruction sets in the field. This allows the same hardware to operate with different instruction sets optimized for different applications, maintaining manufacturing simplicity while achieving adaptability.
2Adaptability or versatility
If reprogrammable array DSP solutions are used with FPGA fabric operating independently as coprocessors, then adaptability and performance are improved, but device complexity and design flow difficulty increase
Solution Approach 1:
The patent merges the FPGA fabric and DSP processor into a unified architecture where the FPGA fabric is subordinate to the DSP. This integration allows the reprogrammable logic to work in conjunction with the DSP core rather than as an independent coprocessor, reducing architectural complexity while maintaining adaptability.
Solution Approach 2:
The patent creates a universal architecture where the FPGA fabric can be programmed to perform various DSP functions directly integrated with the processor. This multi-functional approach eliminates the need for separate coprocessor management and reduces design flow complexity while providing adaptability.
3Productivity
If FPGA fabric is allowed to execute tasks in parallel with the conventional software programmable DSP, then performance is improved, but design complexity and hardware dependency increase
Solution Approach 1:
The patent segments the processing tasks by allowing the FPGA fabric to handle specific reprogrammable instructions while the conventional DSP handles standard instructions. This segmentation enables parallel execution without requiring the entire program to be partitioned, reducing design complexity while improving performance for specific tasks.
Solution Approach 2:
The patent introduces an intermediary instruction set mechanism that mediates between the conventional DSP and the FPGA fabric. This intermediary layer allows seamless integration of reprogrammable instructions into the normal DSP software execution stream without requiring complex parallel task partitioning, simplifying the design flow while enabling performance improvements.
Data Source
AI summary
A software programmable DSP with a field programmable instruction set is described where customized instructions can be created, or certain existing instructions can be modified, at the user's location after taking delivery of the processor. The FPGA fabric used to implement the reprogrammable instructions is restricted to supporting the software-programmable DSP—never functioning as an independent coprocessor—and therefore enabling the reprogrammable instructions to exist in the normal stream of DSP software execution. DSP-type functions implemented in the FPGA fabric are also restricted to being automatically generated such that they are synchronous with the processor clocks—enabling easy conversion to an ASIC. Designs implemented on a die containing a DSP with an FPGA-style reprogrammable instruction fabric may be migrated to a smaller die within a family of DSP die containing hard-wired ASIC instruction fabrics, all members of this ASIC family having common I/O functionality to enable operation in the same system socket.