Request Coalescing Circuit to Reduce Comparator Count on Chips
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Solution Overview
Problem
Existing chip designs require a large number of comparators to coalesce memory access instructions, occupying excessive chip area due to the need for multiple comparisons between each pair of requests.
Innovation Solution
A request coalescing unit utilizing a multiplexer to select a target request, a comparator group to compare it with other requests, and a logic circuit to eliminate duplicates, reducing the number of comparators needed by comparing the target request with all other requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a comparator is set between any two requests to coalesce memory access instructions, then the coalescing function is achieved, but the number of comparators increases and chip area is enlarged
Solution Approach 1:
The patent segments the comparison process into two stages: first comparing requests within groups of 8 (using 4 comparators per group), then comparing the group results (using additional comparators). This segmentation reduces the total number of comparators needed compared to a complete pairwise comparison approach, while still achieving reliable coalescing functionality.
Solution Approach 2:
The patent applies partial comparison action by only comparing requests that are necessary for coalescing. Instead of comparing all possible pairs of requests, the invention compares requests in a systematic manner where each request is compared with others in its group, and then group representatives are compared. This partial action approach reduces the number of comparators while maintaining the coalescing function.
2Measurement precision
If multiple comparators are used to compare any two requests, then all request pairs can be compared, but the circuit complexity and chip area increase
Solution Approach 1:
The comparison process is segmented into multiple rounds where in each round, specific subsets of requests are compared. This segmentation allows the system to achieve complete comparison coverage through multiple simpler comparison stages rather than using a single complex comparator network, thereby reducing circuit complexity while maintaining measurement precision.
Solution Approach 2:
The patent implements periodic comparison action where requests are compared in repeated cycles. In each cycle, requests are compared in groups, and the results are used in subsequent cycles to refine the comparison. This periodic approach allows systematic coverage of all request pairs using a manageable number of comparators, reducing overall circuit complexity while maintaining complete comparison capability.
Data Source
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Figure 3
AI summary
The present disclosure provides a request coalescing method, a cell and a chip, and relates to the field of chip design. The request coalescing unit comprises: a multiplexer, which is configured to determine a target request from a plurality of requests to be coalesced, wherein the target request is one of the plurality of requests selected in accordance with a predetermined condition; and a comparator group, which is coupled to the multiplexer, and is configured to compare the target request with the plurality of requests individually, so as to determine a duplicate request of the plurality of requests that duplicates the target request; a first logic circuit, which is coupled to the multiplexer, for outputting to the multiplexer the remaining requests of the plurality of requests other than the duplicate request and the target request to repeat the comparison process until all of the plurality of requests have completed the comparison; and the multiplexer is further configured to output the target request outside of the request coalescing unit. The request coalescing unit can reduce the chip area occupied by the coalescing unit.