ReRAM Memory Device 3D Stacking Integration
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Solution Overview
Problem
Conventional memory devices face challenges in achieving high integration due to the need for precise lithography and increased lithography step costs, which are exacerbated by the requirement for MOSFETs in memory cells and limited two-dimensional plane structures.
Innovation Solution
The development of a resistive RAM (ReRAM) memory device that uses non-ohmic elements like diodes and variable resistance materials, eliminating the need for MOSFETs and enabling three-dimensional stacking, with a memory cell array structure that includes variable resistance materials on side surfaces of bit lines and a stair-like word line structure in the hook-up-region for enhanced integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOSFETs are used in memory cells to achieve conventional memory functionality, then reliable switching and data storage are achieved, but device size increases and integration density is limited
Solution Approach 1:
The patent extracts and removes the MOSFET component from the memory cell structure, replacing it with a direct variable resistance element connected to bit lines. This elimination of the MOSFET switching device reduces the memory cell area while maintaining functionality through the non-ohmic characteristics of the variable resistance material alone.
Solution Approach 2:
The patent transitions from a planar two-dimensional memory cell layout to a three-dimensional structure by stacking multiple bit line layers and variable resistance material layers vertically. This dimensional change allows higher integration density while maintaining reliable operation through optimized vertical current paths.
2Ease of manufacture
If two-dimensional plane structures are used for memory cell arrays, then fabrication is simplified, but integration density is limited
Solution Approach 1:
The patent extends the memory cell array from a two-dimensional plane to three dimensions by stacking bit lines and variable resistance materials in multiple layers vertically. This enables significantly higher integration density while maintaining manufacturability through standard semiconductor layering and patterning techniques applied in the vertical dimension.
Solution Approach 2:
The patent implements a nested structure where variable resistance materials are positioned on the side surfaces of bit lines, and multiple bit line layers are stacked with insulating films between them. This nested arrangement maximizes the use of vertical space to increase integration density while maintaining ease of manufacture through sequential layer formation.
3Manufacturing precision
If lithography precision is increased to achieve higher integration, then manufacturing precision improves, but production costs increase
Solution Approach 1:
The patent moves integration enhancement from the lateral plane to the vertical dimension through multi-layer stacking. This approach achieves high integration density without requiring proportionally higher lithography precision in the lateral direction, as the vertical layering can be formed using standard thin film deposition and patterning techniques.
Solution Approach 2:
The patent segments the memory cell array into multiple stacked layers of bit lines and variable resistance materials. This segmentation allows each layer to be formed with standard lithography precision while achieving overall high integration through the cumulative effect of multiple layers, rather than requiring extremely high precision in a single planar layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a super-highly integrated memory device with reduced size and increased integration degree, lower power consumption, and improved operation reliability by avoiding negative voltages and optimizing bias conditions, while also reducing the area required for the hook-up-region, thus lowering production costs.
Implementation Method 1
a memory called a resistive RAM (ReRAM), in which each of memory cells is formed with a non-ohmic element typified by a diode and a variable resistance material
Data Source
AI summary
According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.