ReRAM Memory Device Biasing for Off-Leak Current Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Bipolar operation in ReRAM nonvolatile semiconductor memory devices faces challenges in maintaining low off-leak current in unselected memory cells while ensuring sufficient operation current for selected memory cells, leading to high power consumption and sneak currents during erase operations.
Innovation Solution
The implementation of a bias state in the memory cell array where adjacent unselected bit lines or word lines act as assist wiring lines, applying specific voltage levels to reduce the potential difference and hole concentration in selected memory cells, thereby facilitating lower operation voltages and reducing off-leak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a reverse direction bias is applied to unselected memory cells to suppress off-leak current, then off-leak current is kept small, but operation current cannot be supplied to selected memory cells for resistance state switching
Solution Approach 1:
The patent applies different voltage levels to different bit lines or word lines based on their selection status. Selected lines receive voltages that enable operation current flow, while unselected lines receive voltages that suppress off-leak current. This local differentiation of voltage conditions resolves the contradiction by allowing each line to have optimized electrical characteristics for its specific function.
Solution Approach 2:
The patent dynamically adjusts voltage levels applied to bit lines and word lines during different operation phases (read, write, erase). During erase operations, the voltage levels are dynamically changed to facilitate hole injection into the selected memory cell while maintaining suppression of off-leak current in unselected cells, enabling adaptive control of current flow characteristics.
2Power
If high voltage is applied to selected memory cells to ensure sufficient operation current, then resistance state switching is enabled, but off-leak current in unselected memory cells increases
Solution Approach 1:
The patent implements local quality control by applying high voltage only to the selected bit line or word line that intersects with the selected memory cell, while maintaining low voltage on all other unselected lines. This spatial differentiation ensures that high operation current flows only where needed through the selected memory cell, while off-leak current remains suppressed in unselected cells.
Solution Approach 2:
The patent uses the memory cell array structure itself as an intermediary mechanism, where the selected bit line or word line acts as a mediator to deliver high voltage specifically to the target memory cell. The intersecting line structure naturally confines the high voltage effect to the selected cell while unselected cells remain at lower potentials, effectively mediating between power delivery and leak suppression requirements.
3Device complexity
If conventional bipolar operation is performed without assist wiring lines, then device structure is simple, but sneak currents occur and power consumption increases during erase operations
Solution Approach 1:
The patent segments the bit lines or word lines into different voltage zones during erase operations by introducing assist wiring lines. The selected line receives high voltage for hole injection, adjacent unselected lines receive intermediate voltages to suppress sneak currents, and other unselected lines remain at low voltages. This segmentation of voltage levels reduces unnecessary current flow while maintaining the basic memory cell structure.
Solution Approach 2:
The patent applies preliminary voltage conditioning to adjacent unselected bit lines or word lines before the main erase operation. By pre-applying intermediate voltage levels to these assist wiring lines, the patent prepares the electrical environment to prevent sneak currents from flowing through unselected memory cells during the subsequent high-voltage erase pulse, thereby reducing power consumption without structural modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reduced power consumption during resetting operations by enhancing operation current flow in selected memory cells while minimizing sneak currents and off-leak currents in unselected cells.
Implementation Method 1
a rectifier element and a variable resistance element connected in series, wherein one of the first lines is connected to an anode side of the rectifier element and one of the second lines is connected to a cathode side of the rectifier element
Implementation Method 2
The variable resistance element has at least two resistance states, and switching of these resistance states is performed by voltage application to the variable resistance element
Data Source
AI summary
A nonvolatile semiconductor memory device according to an embodiment comprises: a memory cell array including a plurality of memory cells provided at each of intersections of a plurality of first lines and a plurality of second lines; and a control circuit applying a selected first line voltage to a selected first line, an adjacent unselected first line voltage which is larger than the selected first line voltage to an adjacent unselected first line, and an unselected first line voltage which is larger than the adjacent unselected first line voltage to an unselected first line, and applying a selected second line voltage which is larger than the selected first line voltage to a selected second line and an unselected second line voltage which is smaller than the selected second line voltage to an unselected second line.