ReRAM Bit Line Hookup Dummy Wiring for Etching Uniformity
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Solution Overview
Problem
In the manufacturing of ReRAM non-volatile memory devices, the difference in charge-up amounts between adjacent wirings due to dry etching processes leads to dimensional defects and short-circuits, particularly when processing upper-layer wiring with interlayer insulating films, causing issues with the side etching of the upper-layer wiring and falling of the wiring.
Innovation Solution
The implementation of dummy wirings with the same area as the bit lines in the bit line hookup region ensures uniform charge distribution and potential, preventing abnormal etching trajectories and maintaining consistent dimensions during the dry etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dry etching process is used to process word lines or bit lines, then wiring can be formed with precise patterns, but charge-up amounts of wirings become different between adjacent wirings causing dimensional defects and short-circuits
Solution Approach 1:
Dummy wirings are added to adjacent wirings to equalize the total wiring area and charge distribution. By making the sum of actual wiring area plus dummy wiring area equal across all adjacent wirings, the charge-up amounts during dry etching become uniform, preventing dimensional defects and short-circuits while maintaining etching precision
Solution Approach 2:
Dummy wirings are strategically added only to specific adjacent wirings that have smaller areas, rather than modifying all wirings uniformly. This local compensation approach equalizes charge distribution without unnecessarily increasing the complexity of the overall wiring design
2Ease of manufacture
If upper-layer wiring is processed by dry etching, then upper-layer wiring can be formed, but side etching occurs due to curved trajectory of incident particles causing dimensional defects
Solution Approach 1:
By equalizing the total area (actual wiring plus dummy wiring) of adjacent wirings, the charge distribution during dry etching becomes uniform. This prevents the formation of potential differences that cause curved trajectories of incident particles, thereby eliminating side etching and maintaining precise wiring dimensions
3Ease of operation
If contact connection portions are formed at different positions for adjacent wirings, then wiring connections can be established, but wiring lengths become different causing unequal charge-up amounts
Solution Approach 1:
Dummy wirings are added to adjacent wirings with shorter lengths to equalize the total wiring area. This compensation ensures that all adjacent wirings have the same charge capacity during dry etching, maintaining uniform charge distribution and potential while preserving the necessary connection geometry
Solution Approach 2:
The area parameter of dummy wirings is specifically designed to compensate for differences in actual wiring areas. By adjusting the dummy wiring area to match the difference, the total area parameter becomes equal across all adjacent wirings, thereby equalizing charge-up characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents dimensional defects and short-circuits by ensuring uniform charge distribution and potential across all bit lines, maintaining the integrity of the upper-layer wiring and interlayer insulating films during the etching process.
Implementation Method 1
a phenomenon occurs where charge-up amounts of wirings are different. Particularly, in a cross point type memory, after an upper-layer wiring is processed, a memory cell at an intersection point needs to be subsequently processed. However, in the state where the upper-layer wiring is processed, the charge-up amounts are different between the wirings. If an interlayer insulating film embedded between the memory cells is processed by dry etching in this state
Data Source
AI summary
According to one embodiment, there are provided a memory cell forming region, a first wiring hookup region in which first wirings extending in a first direction are formed by being drawn outside of the memory cell forming region, a second wiring hookup region which is disposed in a layer above the first wirings and in which second wirings extending in a second direction are formed by being drawn outside of the memory cell forming region, and a first dummy wiring connected to each of the second wirings. The first dummy wiring is disposed so that a sum of the area of the second wiring and the area of the first dummy wiring becomes the same in the respective second wirings.