ReRAM Integrated in Transistor Drain Via for Footprint Reduction
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Solution Overview
Problem
Resistive random access memory (ReRAM) devices face challenges in area scaling due to uncontrolled electroforming of current conducting filaments, which can lead to variability and increased device footprint when integrated with field effect transistors, particularly in one transistor one resistive random access memory (1T1R) structures.
Innovation Solution
Integrating a resistive switching memory cell directly within the contact via to the drain region of a semiconductor device, including a lower electrode, a switching metal oxide layer, and an upper electrode, which eliminates the need for additional footprint and allows for controlled integration with field effect transistors, such as FinFETs, planar MOSFETs, and vertically oriented transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ReRAM devices are integrated with field effect transistors in conventional structures, then memory functionality is achieved, but device footprint increases and electroforming control deteriorates
Solution Approach 1:
The patent merges the ReRAM device and transistor into a single integrated structure where the ReRAM is formed within the transistor's contact region. The bottom electrode of the ReRAM is formed as part of the transistor's source/drain region, eliminating the need for separate ReRAM contacts and reducing overall device footprint while maintaining electroforming control through the shared structural interface.
Solution Approach 2:
The ReRAM structure is nested within the transistor's contact region. The ReRAM's bottom electrode is formed within the doped semiconductor region of the transistor contact, and the ReRAM's metal oxide layer and top electrode are positioned above it, creating a nested configuration that maximizes space utilization and reduces footprint.
2Area of stationary object
If ReRAM devices are scaled down to reduce footprint, then area is reduced, but electroforming variability increases
Solution Approach 1:
By merging the ReRAM bottom electrode with the transistor's source/drain region, the patent ensures that the electroforming process occurs within a well-defined, controlled semiconductor structure. This integration provides better control over filament formation and reduces variability even as device dimensions are scaled down, because the transistor structure itself provides geometric constraints and doping control.
3Reliability
If additional ReRAM contact structures are added, then electroforming control is improved, but device complexity increases
Solution Approach 1:
The patent eliminates the need for additional separate contact structures by merging the ReRAM bottom electrode with the transistor's source/drain region. This integration reduces structural complexity while maintaining electroforming control, as the transistor's existing contact structure serves dual purposes: as the transistor contact and as the ReRAM bottom electrode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of ReRAM with transistors without additional footprint, enhancing scalability and control over electroforming processes, suitable for non-volatile memory and neuromorphic applications.
Implementation Method 1
One example of non-volatile memory uses variable resistance memory elements that can be set to either low or high resistance states
Implementation Method 2
Resistive random access memory (ReRAM) devices face challenges in area scaling due to uncontrolled electroforming of current conducting filaments
Data Source
AI summary
A method for forming an electrical device including a resistive switching memory cell in combination with a transistor. In some embodiments, the method may include forming a semiconductor device including a source region and a drain region on opposing sides of a channel region. A dielectric layer may be formed over the semiconductor device. A drain via opening may be formed through the dielectric layer to expose an upper surface of the drain region of the semiconductor device. A resistive random access memory cell is formed in the drain via opening in direct contact with the drain region of the semiconductor device.