ReRAM Compute-in-Memory Dual-Sign Encoding for Lower Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Resistive random-access memory (ReRAM) cells in compute-in-memory devices for machine learning models face high power consumption due to a high occurrence of low-resistive states, which require large current access for bit '1' operations.
Innovation Solution
Encoding weights in a dual sign bit format to reduce the occurrence of low-resistive states by converting the most significant magnitude bit to a sign bit, thereby reducing the number of low-resistive memory cells and lowering power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If weights are stored in ReRAM cells using conventional encoding, then the memory can store machine learning model weights, but the power consumption increases due to high occurrence of low-resistive states requiring large current access
Solution Approach 1:
The patent applies parameter changes by transforming the encoding format of weights from conventional two's complement to dual sign bit format. This parameter change in the representation method fundamentally alters the distribution of resistive states in ReRAM cells, reducing the occurrence of low-resistive states and thereby decreasing the current required for bit line access and overall power consumption.
2Use of energy by stationary object
If dual sign bit format is used to encode weights, then the occurrence of low-resistive states is reduced and power consumption is lowered, but the device complexity increases due to additional encoding and decoding circuits
Solution Approach 1:
The patent applies segmentation by dividing the weight encoding into distinct components: a sign bit and magnitude bits. This segmentation allows for specialized handling of sign information separate from magnitude information, enabling efficient dual sign bit encoding that reduces low-resistive state occurrences while maintaining manageable circuit complexity through structured organization of encoding/decoding operations.
3Quantity of substance
If the most significant magnitude bit is converted to a sign bit in dual sign bit format, then the number of low-resistive memory cells is reduced, but the manufacturing precision requirements increase for bit line current control
Solution Approach 1:
The patent applies feedback mechanisms in the decoding process where the sign bit information is used to control and adjust the bit line current during read operations. This feedback-based current control compensates for variations in memory cell characteristics, maintaining manufacturing precision while benefiting from the reduced low-resistive state distribution provided by dual sign bit encoding.
Data Source
AI summary
A memory device is provided, comprising an encoder circuit, a memory array and an accumulator circuit. The encoder circuit converts a first bit of each of weights into a sign bit to generate encoded weights according to flag data. The memory array comprises memory cells. The memory cells arranged in a same column store bits, of the encoded weights and the flag data, having the same index number. The memory array performs a compute-in-memory (CIM) operation to the encoded weights and inputs to generate a plurality of CIM results. Each of the plurality of CIM results corresponds to a column of the memory array. The accumulator circuit decodes the CIM results according to the flag data to generate decoded CIM results.