Compact ReRAM PFGA Cell Circuit Mitigates Gate Stress
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Solution Overview
Problem
Designing ReRAM configuration memory cells for FPGAs is hindered by the need for a transition region due to photolithographic requirements, which is not compatible with devices operating at different voltages, and results in elevated gate stress for programming transistors.
Innovation Solution
A push-pull ReRAM cell circuit with two programming transistors and a switch transistor having the same pitch and channel length, using a thicker dielectric to mitigate gate stress and allow higher VCC operation, eliminating the transition region and ensuring compatibility across different voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithographic production is used with different pitch requirements for programming transistors and switch transistors, then manufacturing capability is achieved, but transition region is required which increases device area and reduces layout efficiency
Solution Approach 1:
The patent applies local quality by giving different gate dielectric thicknesses to different transistor types within the same circuit. Programming transistors use a first gate dielectric thickness optimized for withstanding high programming voltages, while switch transistors use a second gate dielectric thickness optimized for low-leakage switching operation. This localized differentiation allows each transistor type to be optimized for its specific function without requiring transition regions, thereby reducing overall device area while maintaining manufacturability.
2Reliability
If programming transistors use thicker gate dielectric to withstand programming voltages, then programming capability is achieved, but switch transistors experience elevated gate stress during programming
Solution Approach 1:
The patent resolves this contradiction by implementing local quality through differentiated gate dielectric thicknesses. Programming transistors are equipped with a first gate dielectric having a thickness designed to withstand high programming voltages (e.g., 1.8V to 3.6V), while switch transistors use a second gate dielectric with optimized thickness for switching operations. This localized optimization ensures that programming transistors can handle high voltages without compromising switch transistor reliability, as each type has dielectric thickness tailored to its specific voltage requirements.
Solution Approach 2:
The patent applies segmentation by dividing the gate dielectric structure into two distinct types: a first gate dielectric for programming transistors and a second gate dielectric for switch transistors. This segmentation allows independent optimization of dielectric thickness for each transistor type, enabling programming transistors to withstand high programming voltages while protecting switch transistors from elevated gate stress during programming operations.
3Area of stationary object
If all transistors use the same pitch and channel length, then transition region is eliminated and layout efficiency is improved, but compatibility with different voltage operations becomes difficult
Solution Approach 1:
The patent resolves this contradiction through local quality by assigning different gate dielectric thicknesses to different transistor types while maintaining uniform pitch and channel length across all transistors. Programming transistors use a first gate dielectric thickness optimized for high-voltage programming operations, while switch transistors use a second gate dielectric thickness optimized for low-voltage switching. This localized differentiation enables all transistors to share the same geometric dimensions (pitch and channel length), eliminating the need for transition regions and improving layout efficiency, while simultaneously maintaining compatibility with different voltage operations through dielectric thickness variation.
Data Source
AI summary
A push-pull resistive random access memory cell circuit includes an output node, a word line, a first bit line, and a second bit line. A first resistive random access memory device is connected between the first bit line and the output node and a second resistive random access memory device is connected between the output node and the second bit line. A first programming transistor has a gate connected to the word line, a drain connected to the output node, and a source. A second programming transistor has a gate connected to the word line, a drain connected to the source of the first programming transistor, and a source. The first and second programming transistors have the same pitch, the same channel length, and the same gate dielectric thickness, the gate dielectric thickness chosen to withstand programming and erase potentials encountered during operation of the push-pull ReRAM cell circuit.