ReRAM Pillar Buffer Layer for Leakage Current Control
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Solution Overview
Problem
Current non-volatile memory devices face challenges in scaling down memory capacity per unit surface area, and existing techniques for vertically forming memory cells do not effectively address the need for efficient interconnection and resistance variability in ReRAM devices.
Innovation Solution
A semiconductor device design featuring a stack of word lines, bit lines, and variable resistors with a pillar structure, including a buffer layer and diode layer, and a conductive pad, which allows for vertical interconnection and variable resistance material between the word lines and bit lines, enhancing electrical properties and preventing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically forming memory cells is implemented to scale down device size, then memory capacity per unit surface area is improved, but interconnection complexity and resistance variability worsen
Solution Approach 1:
The memory device is segmented into multiple vertical stacks, each containing word lines, bit lines, and variable resistors arranged in distinct layers. This segmentation allows independent formation and control of each memory cell stack, simplifying the interconnection scheme while achieving high density through vertical stacking.
Solution Approach 2:
The patent transitions from planar interconnection to three-dimensional vertical interconnection. Word lines and bit lines are arranged in vertical stacks with variable resistors positioned between them, enabling memory cells to be accessed through vertical current paths rather than lateral connections, thereby reducing interconnection complexity.
2Area of stationary object
If vertically forming memory cells is implemented to scale down device size, then memory capacity per unit surface area is improved, but resistance variability worsens
Solution Approach 1:
Buffer layers with specific material compositions are placed at localized positions between the variable resistors and the molding layers. These buffer layers have tailored electrical and mechanical properties that locally compensate for stress and dimensional variations, thereby reducing resistance variability in the variable resistors without affecting the overall vertical scaling.
Solution Approach 2:
The patent employs composite structures combining variable resistors made of phase-change materials or resistive materials with buffer layers of different materials (e.g., silicon oxide, silicon nitride). This composite approach allows optimization of each layer's properties to maintain consistent resistance characteristics despite manufacturing variations.
3Reliability
If buffer layers are added between pillar and molding layers, then reliability is improved by preventing leakage current, but device complexity increases
Solution Approach 1:
Buffer layers are introduced as intermediary structures between the conductive pillar/electrode and the molding layers. These buffer layers act as electrical isolators that prevent leakage current paths while maintaining the structural integrity of the vertical stack. The buffer layers are formed using standard deposition techniques and integrated into the existing manufacturing process.
4Reliability
If diode layer and variable resistance material are interposed between pillar and horizontal interconnection line, then electrical properties are improved, but manufacturing complexity increases
Solution Approach 1:
The diode layer and variable resistance material are merged into a single vertical stack structure between the horizontal interconnection lines and the pillar. This combined structure is formed through sequential deposition and patterning steps that are integrated into the standard ReRAM fabrication process, avoiding the need for separate manufacturing operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design improves the electrical properties of non-volatile memory devices by enabling efficient vertical interconnection and resistance variability, leading to improved memory capacity and reliability.
Implementation Method 1
variable resistance material and a diode layer interposed between the pillar and the horizontal interconnection line
Implementation Method 2
variable resistance material and a diode layer interposed between the pillar and the horizontal interconnection line
Data Source
AI summary
A non-volatile memory device includes a lower molding layer, a horizontal interconnection line on the lower molding layer, an upper molding layer on the horizontal interconnection line, pillars extending vertically through the upper molding layer, the horizontal interconnection line, and the lower molding layer, and a buffer layer interposed between the pillars and the molding layers. The device also includes variable resistance material and a diode layer interposed between the pillars and the horizontal interconnection line.