3D ReRAM Reference Bit Line Noise Cancellation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in enhancing reliability due to noise interference from select gate lines and global bit lines, which can lead to incorrect data sensing in resistive random access memory (ReRAM) systems.
Innovation Solution
The implementation of a three-dimensional stacked ReRAM configuration with a reference bit line arranged in the same layer as the global bit line, having similar interconnect shape and capacitance characteristics, allows for common-mode noise cancellation by the sense circuit, thereby reducing the impact of noise from select gate lines and improving data reading accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a reference bit line is added to match the global bit line configuration, then noise cancellation capability is improved, but device complexity increases
Solution Approach 1:
The patent creates a reference bit line that is a simplified copy of the global bit line structure. The reference bit line is positioned adjacent to the global bit line and has similar capacitance characteristics, allowing it to replicate the noise environment without requiring identical complexity. This copying approach enables common-mode noise cancellation while maintaining practical device complexity levels.
Solution Approach 2:
The reference bit line acts as an intermediary element between the noise source (select gate lines) and the sensing circuit. By providing a dedicated reference path that experiences similar noise but carries no signal, the system can subtract the noise component from the actual signal path, effectively isolating the true data signal from interference.
2Reliability
If the reference bit line is positioned close to the global bit line for noise matching, then noise cancellation is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the capacitance parameter of the reference bit line by adjusting its width, length, or dielectric properties to match the global bit line's capacitance characteristics. This parameter matching ensures that the reference bit line experiences equivalent noise coupling without requiring extremely tight positional tolerances, thereby relaxing manufacturing precision requirements while maintaining effective noise cancellation.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes: a first insulating layer; a global bit line and a reference bit line provided on the first insulating layer; a second insulating layer provided on the global bit line and the reference bit line; a select gate line provided on the second insulating layer; a first transistor provided on the global bit line; a local bit line coupled to the first transistor; first and second memory cells; and a sense amplifier. The global bit line and the reference bit line three-dimensionally intersect the select gate line via the second insulating layer.