ReRAM Reset Reliability via Bipolar Pulse Filament Separation
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in reliably transitioning resistive random access memory (ReRAM) cells between high and low resistance states during reset operations, often resulting in reset failures due to insufficient Joule heat generation and vacancy concentration at the electrode interface.
Innovation Solution
The semiconductor memory device employs a control circuit that applies a first pulse with a specific polarity to initiate filament formation and then a second pulse with inverse polarity to separate the filament, ensuring efficient Joule heat generation and increased vacancy concentration for reliable transition between resistance states, thereby preventing reset failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single pulse is applied to transition the memory cell between resistance states, then the operation is simple and fast, but the transition reliability is insufficient due to inadequate Joule heat generation and vacancy concentration
Solution Approach 1:
The reset operation is segmented into two distinct pulses: a first pulse with a first polarity to generate Joule heat and concentrate vacancies, and a second pulse with a second polarity (opposite to the first) to separate the filament and achieve reliable reset. This segmentation allows each pulse to perform a specific function that collectively solves the reliability problem without requiring complex additional components.
2Reliability
If insufficient Joule heat is generated during the reset operation, then the energy consumption is low, but the filament separation is incomplete resulting in reset failures
Solution Approach 1:
The first pulse is applied as a preliminary action to generate sufficient Joule heat and concentrate vacancies at the electrode interface before the second pulse is applied for filament separation. This preliminary heating action ensures that when the second pulse is applied, the filament can be completely and reliably separated, avoiding reset failures while managing energy consumption through controlled pulse parameters.
3Reliability
If vacancy concentration at the electrode interface is insufficient, then the material consumption is low, but the resistive state transition is unreliable
Solution Approach 1:
The first pulse changes the physical parameters at the electrode interface by generating Joule heat that increases temperature and concentrates vacancies. This parameter change (temperature increase through Joule heating) directly addresses the vacancy concentration issue, enabling reliable resistive state transitions without requiring excessive material consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable transition between high and low resistance states, reducing reset failure occurrences and maintaining the desired resistance state even after voltage reduction, thus enhancing the memory device's operational reliability.
Implementation Method 1
insufficient Joule heat generation and vacancy concentration at the electrode interface
Implementation Method 2
The memory cell is provided between the first electrode and the second electrode, and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to perform transition of a resistive state of the memory cell.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell is provided between the first electrode and the second electrode, and includes a metal film and a resistance change film. The control circuit applies a voltage between the first electrode and the second electrode to transition a resistive state of the memory cell. The control circuit performs a first reset operation by applying a first pulse having a voltage of a first polarity to the memory cell, and applying a second pulse having a voltage of a second polarity that is an inverse of the first polarity to the memory cell after applying the first pulse.