ReRAM Memory Cell Array with Select Transistors
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Solution Overview
Problem
The increasing miniaturization of semiconductor memory devices poses challenges in achieving higher integration levels while maintaining effective selectivity and reducing leak currents, particularly in ReRAM structures where variable resistance elements are used, due to the complexity of manufacturing and the need for precise control over resistance states.
Innovation Solution
The semiconductor memory device employs a configuration with stacked conductive layers, select transistors, and variable resistance films, where the conductive layers are formed in comb tooth shapes to reduce the number of contacts and improve selectivity, and the variable resistance films are strategically placed to function as both storage elements and gate insulating films, allowing for independent control and reducing leak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the variable resistance element is provided at an intersection of a word line and a bit line in a ReRAM structure, then higher integration density is achieved, but manufacturing complexity increases and control over resistance states becomes more difficult
Solution Approach 1:
The memory cell array is segmented into multiple blocks, with each block containing a specific arrangement of variable resistance elements, select transistors, and conductive layers. This segmentation allows for modular manufacturing and simplifies the control of resistance states by isolating different memory cell groups.
Solution Approach 2:
Different regions of the memory cell array employ different configurations of select transistors and conductive layers tailored to local requirements. For example, first select transistors are positioned below the variable resistance element while second select transistors are positioned above, allowing optimized control of resistance states in different local areas.
2Ease of manufacture
If conventional select transistor configurations are used in ReRAM structures, then manufacturing is simpler, but selectivity deteriorates and leak currents increase
Solution Approach 1:
The select transistor is merged with the variable resistance element structure, where the gate of the select transistor is formed using the same conductive layer that serves as an electrode for the variable resistance element. This merging improves selectivity by ensuring precise control of current flow through the memory cell while maintaining manufacturing simplicity through shared fabrication steps.
Solution Approach 2:
The conductive layer serves multiple functions: it acts as a gate electrode for the select transistor and simultaneously as an electrode for the variable resistance element. This multi-functionality reduces the number of separate components needed, maintaining ease of manufacture while improving selectivity through integrated control.
3Reliability
If the gate of the select transistor is formed using the same conductive layer as the variable resistance element electrode, then selectivity is improved and leak currents are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The conductive layer is formed and positioned with high precision during the preliminary stages of manufacturing, before the variable resistance element material is deposited. This preliminary action ensures that the gate and electrode functions are aligned from the outset, reducing the need for subsequent precision adjustments and maintaining manufacturing feasibility.
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a memory cell array that includes a plurality of memory cells. The memory cell array comprises: a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction intersecting the first direction; a second conductive layer extending in the first direction; a variable resistance film provided at intersections of the plurality of first conductive layers and the second conductive layer; a first select transistor disposed closer to a side of the substrate than a lowermost layer of the plurality of first conductive layers, the first select transistor including a first select gate line intersecting the second conductive layer; a third conductive layer that extends in a third direction intersecting the second direction and is connected to a lower end of the second conductive layer via the first select transistor; and a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the first direction, the second select transistor including a second select gate line intersecting the second conductive layer.