ReRAM Source Line Drivers for Voltage Management

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Solution Overview

Problem

Conventional resistance random access memory (ReRAM) arrays face challenges in efficiently managing multiple voltage levels for different operations, leading to difficulties in handling high-density arrays and potential performance degradation due to power burdens.

Innovation Solution

A memory structure comprising a matrix of memory cells with resistive memory devices and transistors, where source lines are driven by source line drivers to apply specific voltage levels for SET and RESET operations, and bit lines are grouped to reduce power consumption and enhance operational efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple voltage levels are applied for different operations in conventional ReRAM arrays, then SET and RESET operations can be performed, but power consumption increases and performance degrades in high-density arrays

Engineering Contradiction:
Improveoperation voltage levelsVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The source lines are segmented into multiple groups, with each group driven by an independent source line driver. This segmentation allows different voltage levels to be applied to different source line groups simultaneously, enabling efficient management of multiple operations (SET, RESET, READ) in high-density arrays without excessive power consumption, as only the required source line groups are activated for each operation

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If source lines are shared by multiple word lines to increase density, then array density improves, but voltage management complexity increases

Engineering Contradiction:
Improvearray densityVSAvoidvoltage management
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The source line driver is designed with dynamic control capability to selectively apply different voltage levels to different source line groups based on the operation being performed. This dynamic voltage management allows source lines to be shared by multiple word lines while maintaining simplified control logic, as the driver automatically adjusts voltages according to the selected memory cell location and operation type

Inventive Principle:
Principle #15Dynamics

3Reliability

If source line driver pulls up source line to first voltage level for RESET operation, then RESET function is achieved, but power consumption increases compared to grounding

Engineering Contradiction:
ImproveRESET operationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

Different voltage levels are applied to different source line groups based on the specific operation and memory cell location. For RESET operations, only the source line group corresponding to the selected memory cell is pulled up to the first voltage level, while other source line groups are grounded. This localized voltage application achieves reliable RESET function while minimizing overall power consumption in the high-density array

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20160049196A1Memory with specific driving mechanism applied on source line
Publication Date: 2016.02.18 WINBOND ELECTRONICS CORP
  • US20160049196A1 patent drawing
  • US20160049196A1 patent drawing
  • US20160049196A1 patent drawing

AI summary

An embodiment of the invention provides a memory. The memory includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a memory cell array. The memory cell array has a plurality of memory cells disposed at the intersections of the word and bit lines to form a matrix of rows and columns, wherein each memory cell comprises a resistive memory device and a transistor. The source lines are each disposed between two word lines, wherein each source line is coupled to source terminals of the transistors. When a RESET operation is applied to a selected memory cell, the voltage level of the source line is pulled up to a first voltage level, and when another operation is applied to the selected memory cell, the source line is grounded.