ReRAM Source Line Segmentation for Read Speed
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Solution Overview
Problem
The slow reading speed in resistive random access memory (ReRAM) systems is due to the large RC loading of the read source line, which is exacerbated by the connection of multiple memory cells, making it difficult to improve the read current and reduce parasitic capacitance effectively.
Innovation Solution
The source line is divided into smaller segments, and a two-transistor (2T) driving cell is shared by fewer memory cells to amplify the current, reducing the loading and improving reading speed, while maintaining a small cell area penalty and enhancing the sense amplifier's read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory cells are connected to the read source line, then storage capacity is improved, but reading speed deteriorates due to large RC loading
Solution Approach 1:
The read source line is divided into multiple segments, each serving a subset of memory cells. This segmentation reduces the RC loading on each segment, allowing faster reading speeds while maintaining the ability to access multiple cells through the segmented structure.
2Quantity of substance
If the read source line is made longer to connect more cells, then storage capacity is improved, but parasitic capacitance increases
Solution Approach 1:
By segmenting the read source line into shorter segments, each segment has reduced parasitic capacitance. The overall system can still connect more memory cells through the segmented architecture, achieving higher storage capacity without the capacitance penalty of a single long source line.
3Speed
If current amplification is added to improve reading speed, then reading speed is improved, but device complexity increases
Solution Approach 1:
The current amplification function is merged with the existing memory cell structure by using additional memory cells as amplifiers. This integration approach improves reading speed through current amplification while minimizing the increase in device complexity, as the amplifiers are part of the standard cell array rather than separate external components.
Data Source
AI summary
A resistive random access memory (ReRAM) apparatus is provided. The ReRAM apparatus includes a plurality of memory cells, each of the memory cells comprises a transistor and a resistor; a bit line connected to a first terminal of the resistor of each of the memory cells; a local source line connected to a source electrode of the transistor of each of the memory cells; and a driving cell connected between the local source line and a global source line. A method for operating the ReRAM apparatus is also provided.