ReRAM Write Voltage Step Control for Peak Current Reduction
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Solution Overview
Problem
In resistance-change memory devices, such as ReRAM, writing a SET state to multiple memory cells simultaneously leads to high peak current consumption, which raises the potential of the word line, making it difficult to write data to other cells, and results in a large leak current in half-selected memory cells.
Innovation Solution
A semiconductor storage device with a plurality of signal lines and drivers that gradually increase the SET voltage in write loops, allowing for partial or gradual transition of memory cells to a SET state, while suppressing the peak current by varying the step-up width of the SET voltage in each write loop, and incorporating a current detector to stop power supply when the current exceeds a predetermined value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a SET state is written to a large number of memory cells simultaneously, then data writing speed is improved, but the peak consumption current is increased
Solution Approach 1:
The patent segments the simultaneous write operation into multiple write loops, where memory cells are divided into groups that are written in sequential phases. Each write loop targets a subset of memory cells, thereby distributing the current demand over time and reducing peak consumption current while maintaining overall writing throughput.
Solution Approach 2:
The patent implements periodic write operations with multiple write loops, where each loop performs a write operation followed by a verify operation. This periodic structure allows current consumption to be spread across multiple time periods, preventing simultaneous high current draw from all memory cells while achieving complete data writing through repeated cycles.
2Productivity
If a SET state is written to multiple memory cells connected to a selected word line, then data writing capability is improved, but the word line potential is raised making subsequent writes difficult
Solution Approach 1:
The patent segments the set of memory cells connected to a selected word line into multiple groups, writing to each group in separate write loops. This segmentation prevents excessive current accumulation on the word line that would raise its potential and compromise subsequent write operations, while still achieving comprehensive data writing across all cells.
Solution Approach 2:
The patent performs preliminary write operations to a first group of memory cells in earlier write loops before addressing the second group. This preliminary action allows the system to manage word line potential buildup progressively, ensuring that each write operation occurs under favorable electrical conditions while ultimately achieving complete data writing.
3Productivity
If a large current flows in memory cells to write SET state, then writing speed is improved, but half-selected memory cells experience large leak current
Solution Approach 1:
The patent segments the write operation so that only a subset of memory cells is targeted in each write loop, with half-selected cells experiencing reduced voltage stress. This segmentation reduces the leak current in half-selected cells compared to simultaneous writes, while maintaining acceptable writing speed through multiple efficient write cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the peak current flowing in memory cells, minimizes disturbance to half-selected cells, and ensures reliable writing of data by smoothing the consumption current across write loops, thereby improving data writing efficiency and reducing power consumption.
Implementation Method 1
A resistance-change memory such as a ReRAM stores data in memory cells by bringing the memory cells to a high-resistance state or a low-resistance state. For example, when a SET voltage is applied to a bit line while keeping a word line at a low-level voltage Vss, a relevant memory cell is changed from a high-resistance state (a RESET state) to a low-resistance state (a SET state).
Data Source
AI summary
A memory includes first signal-lines, second signal-lines and resistance-change memory cells. First and second drivers can supply power to the first and second signal-lines, respectively. The second driver increases a voltage of a selected second signal-line in a write-loop higher than that in a previous write-loop. The write-loop includes a write operation and a verify operation. A voltage increase width of the selected second signal-line at a time of transition from a first write-loop to a second write-loop is larger than a voltage increase width of the selected second signal-line at a time of transition from the second write-loop to a third write-loop. A voltage increase width of the selected second signal-line at a time of transition from the second write-loop to the third write-loop is smaller than a voltage increase width of the selected second signal-line at a time of transition from the third write-loop to a forth write-loop.