ReRAM Upper-Layer Wiring Dummy Structures for Dry Etching Charge-Up
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Solution Overview
Problem
In the manufacturing of non-volatile memory devices, particularly ReRAM, the differential charge-up amounts between adjacent wirings during the dry etching process lead to dimensional defects and short-circuits due to the curved trajectory of incident particles and side etching of the interlayer insulating film, especially when processing upper-layer wirings.
Innovation Solution
The method involves forming dummy wirings that equalize the charge-up amounts of upper-layer wirings by connecting their ends in a line-and-space shape, ensuring they are at the same potential, thereby preventing defects during dry etching and maintaining uniform etching trajectories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dry etching is performed on upper-layer wirings with different charge-up amounts, then wiring connections are formed, but dimensional defects occur due to curved particle trajectories
Solution Approach 1:
Dummy wirings are introduced to equalize the charge-up amounts of adjacent upper-layer wirings during dry etching. By providing additional conductive paths through dummy wirings, all wirings in the upper layer reach the same electric potential, ensuring uniform charge distribution and preventing curved particle trajectories that cause dimensional defects.
Solution Approach 2:
Dummy wirings act as intermediary elements that mediate the charge-up difference between adjacent functional wirings. These dummy structures serve as electrical bridges that balance the potential distribution, allowing the dry etching process to proceed with uniform particle trajectories without affecting the functional wiring connections.
2Ease of manufacture
If dry etching is performed on interlayer insulating film under upper-layer wirings, then layer separation is achieved, but short-circuits occur due to side etching
Solution Approach 1:
By equalizing the charge-up amounts of upper-layer wirings through dummy wirings, the electric potential distribution becomes uniform across the entire upper layer. This prevents localized charge accumulation that would cause asymmetric particle trajectories and unwanted side etching of the interlayer insulating film, thereby avoiding short-circuits while maintaining ease of layer separation.
3Measurement precision
If wiring lengths are adjusted to match memory cell array region, then connection accuracy is improved, but charge-up amounts become different between adjacent wirings
Solution Approach 1:
The invention decouples the relationship between wiring length and charge-up amount by introducing dummy wirings. Functional wirings can be optimized for connection accuracy with appropriate lengths, while dummy wirings compensate for charge-up differences by providing additional conductive paths, ensuring all wirings reach equal potential and enabling reliable etching processes.
Solution Approach 2:
The wiring system is segmented into functional wirings and dummy wirings with distinct roles. Functional wirings are optimized for electrical connection and positioning accuracy, while dummy wirings are dedicated to charge-up equalization. This segmentation allows independent optimization of both connection accuracy and etching reliability without compromise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively suppresses dimensional defects and short-circuits by equalizing the potential of upper-layer wirings, ensuring accurate processing and preventing defects caused by curved particle trajectories during dry etching.
Implementation Method 1
Next, dry etching is performed so that the memory-layer constituting layer and the first wiring material layer are etched to form a first pattern
Implementation Method 2
a phenomenon occurs where charge-up amounts of wirings are different
Data Source
AI summary
According to one embodiment, dry etching is performed so that an upper-layer wiring material layer, a memory-layer constituting layer, and an interlayer insulating film are processed to form a pattern including a line-and-space pattern extending in a second direction and a dummy pattern connecting line patterns constituting the line-and-space pattern in a memory cell formation region and an upper-layer wiring hookup region. Then, the dummy pattern is removed.