Resampled Frequency Divider for Low Phase Noise PLL Signals
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Solution Overview
Problem
Frequency dividers in PLL circuits produce signals with higher noise levels due to significant jitter, resulting in high phase noise, necessitating a reduced noise frequency divider system and method.
Innovation Solution
A reduced-noise frequency divider system that includes a frequency divider and a resampler, where the resampler uses the input signal as a sampling clock to reduce noise in the divided signal, potentially incorporating a filter and dual resampler with a delay module to further simplify and stabilize the output waveform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a frequency divider is used to produce lower-frequency signals from higher-frequency signals, then the frequency division function is achieved, but the noise level and phase noise increase significantly
Solution Approach 1:
A resampler is introduced as an intermediary component between the frequency divider and the output. The resampler uses the original high-frequency input signal as a sampling clock to resample the divided low-frequency signal, thereby removing the jitter and phase noise introduced by the frequency divider while preserving the frequency division function.
Solution Approach 2:
The system is segmented into two distinct functional blocks: a frequency divider that performs the frequency division operation, and a resampler that performs the noise reduction operation. This segmentation allows each component to perform its specialized function optimally without interfering with the other.
2Adaptability or versatility
If a frequency divider is used in PLL circuits, then frequency control capability is improved, but the output signal exhibits high phase noise
Solution Approach 1:
The resampler acts as a mediator that takes the phase-noisy divided signal and the clean original input signal, and produces a clean divided output signal by using the original signal's timing information to resample the divided signal, thereby eliminating phase noise while maintaining frequency control capability.
3Speed
If jitter is introduced by frequency divider transitions, then frequency division is achieved, but the signal quality deteriorates with high noise levels
Solution Approach 1:
The resampler uses the original high-precision input signal as a sampling clock to resample the divided signal, thereby transferring the precise timing information from the original signal to the divided signal and eliminating the jitter introduced by the frequency divider's transitions.
Data Source
AI summary
Embodiments of a reduced noise reduction system (“RNFDS”) include a frequency divider and a resampler in signal communication with the frequency divider. The frequency divider receives an input signal and, in response, produces a divided signal. The input signal has a first frequency and the divided signal has a second frequency, different from the first frequency. The resampler receives the input signal and the divided signal, and resamples the divided signal using the input signal as a sampling clock signal to produce a resampled output signal. The frequency divider imposes edge jitter on the divided signal. Resampling the divided signal produces the resampled output signal with an edge jitter comparable with that of the input signal.