Re-sampler for Clock Rate Mismatch in Data Transmission

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Solution Overview

Problem

Existing electronic devices experience delays when transmitting data between devices with different communication protocols due to clock rate differences, leading to potential communication errors and streaming interruptions.

Innovation Solution

An electronic device with a first communication unit to receive data from a first external device, a re-sampler to adjust the data based on clock rate differences, and a second communication unit to transmit the re-sampled data to a second external device using a different protocol, ensuring synchronization and preventing delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transmitted directly between devices with different clock rates, then transmission speed is maintained, but timing synchronization deteriorates causing delays

Engineering Contradiction:
Improvedata transmission speedVSAvoidtiming synchronization
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent introduces a buffer memory as an intermediary component between the first communication unit and the second communication unit. This buffer temporarily stores received data packets and releases them at the appropriate timing to match the second device's clock rate, thereby maintaining both transmission speed and timing synchronization without direct device-to-device timing coupling.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data is re-sampled to match clock rate differences, then timing synchronization is improved, but device complexity increases

Engineering Contradiction:
Improvetiming synchronizationVSAvoidsignal processing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the timing parameter of data packets by storing them in a buffer memory for a calculated duration. This parameter change (time delay) compensates for clock rate differences between devices, achieving synchronization through temporal adjustment rather than complex signal processing or clock rate conversion.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If buffer memory is used to synchronize data timing, then timing synchronization is improved, but data transmission delay increases

Engineering Contradiction:
Improvetiming synchronizationVSAvoiddata transmission delay
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial buffering by calculating and implementing only the minimum necessary buffer duration required to compensate for clock rate differences. This partial action approach achieves sufficient timing synchronization without introducing excessive delay, optimizing the trade-off between synchronization reliability and transmission speed.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS12200094B2Electronic device and method for controlling same
Publication Date: 2025.01.14 LG ELECTRONICS INC
  • US12200094B2 patent drawing
  • US12200094B2 patent drawing
  • US12200094B2 patent drawing

AI summary

Disclosed are an electronic device and a method for controlling same. The disclosed electronic device re-samples data received from a first external electronic device, on the basis of the difference in speed between the clock speed of the first external electronic device and the clock speed of the disclosed electronic device, and transmits the re-sampled data to a second external electronic device.