Resampling Circuit Reduces Periodic Noise in IMU Data

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Solution Overview

Problem

Existing inertial measurement units (IMUs) and physical quantity sensor units face issues with periodic noise in output data due to asynchronous sampling rates, leading to lower quality measurement data when converting sampling rates.

Innovation Solution

A resampling circuit that converts data from a higher sampling clock to an external trigger clock, using a high-frequency clock to calculate representative values with improved time resolution, reducing periodic noise by filtering and averaging techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If resampling is performed by interpolation with the lowest common multiple of two sampling rates, then the sampling rate conversion is achieved, but periodic noise is generated in output data due to asynchronous sampling rates

Engineering Contradiction:
Improvesampling rate conversionVSAvoidperiodic noise
Core Design Contradiction:
SpeedVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a high-frequency clock signal as an intermediary mediator between the first clock signal and the second clock signal. By performing calculations at the higher third clock frequency and then averaging the results, the system mediates the asynchronous sampling rates without generating periodic noise. This intermediary approach allows accurate resampling while eliminating the harmful periodic noise that would otherwise be generated by direct interpolation methods.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If A/D conversion is carried out at a higher frequency than the output rate of measurement data, then time resolution is improved, but a resampling circuit is required to convert sampling rates

Engineering Contradiction:
Improvetime resolutionVSAvoidresampling circuit
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges the resampling function into the existing calculation processing pipeline by performing accumulation and averaging operations using the high-frequency clock data. Instead of requiring a separate dedicated resampling circuit, the system combines the high-frequency A/D conversion with the calculation processing, using the same processing units to both calculate physical quantities and perform sampling rate conversion through accumulation and averaging.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11187716B2Resampling circuit, physical quantity sensor unit, inertial measurement unit, and structure monitoring device
Publication Date: 2021.11.30 SEIKO EPSON CORP
  • US11187716B2 patent drawing
  • US11187716B2 patent drawing
  • US11187716B2 patent drawing

AI summary

A resampling circuit converts first data updated synchronously with a first clock signal into second data updated synchronously with a second clock signal asynchronous with the first clock signal and outputs the second data. The resampling circuit calculates and outputs the second data with a time resolution of a third clock signal having a higher frequency than the first clock signal and the second clock signal, based on the first data.