Rescheduling Failed Memory Requests in Barrel-Multithreaded Processors
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Solution Overview
Problem
In chiplet systems, particularly in barrel-multithreaded processors, issues arise when a thread attempts to issue a memory request that fails due to hazards, leading to pipeline stalls and additional circuitry requirements, which increase latency and performance costs for all allocated threads.
Innovation Solution
The solution involves rescheduling threads that are denied memory requests as if the request was successful by placing them in an interim queue and using the existing memory response path, without additional circuitry, allowing hazards to be cleared without penalty to other threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional pipeline stall approach is used for failed memory requests, then hazard clearance is achieved, but latency increases and performance deteriorates for all allocated threads
Solution Approach 1:
The patent segments the thread rescheduling process into two distinct paths: a successful memory request path and a failed memory request path. By separating these paths, the system can handle failed requests without stalling the entire pipeline, thus clearing hazards while maintaining performance for other threads.
Solution Approach 2:
The patent introduces an intermediary mechanism (the bypass path through memory response path circuitry) that allows threads with failed memory requests to be rescheduled without going through the traditional stall resolution process. This intermediary path enables hazard clearance while avoiding the performance penalty of pipeline stalls.
2Reliability
If additional circuitry is added to handle failed memory requests, then thread rescheduling reliability is improved, but device complexity increases
Solution Approach 1:
The patent makes the memory response path circuitry multi-functional by enabling it to handle both successful memory requests and failed memory requests. By configuring the same circuitry to serve dual purposes, the system achieves improved thread rescheduling reliability without adding new hardware components.
Solution Approach 2:
The system uses its existing memory response path circuitry to handle failed memory requests, allowing the hardware to serve itself without external assistance. The same circuitry that handles successful requests is repurposed to handle failed requests, eliminating the need for additional dedicated circuitry.
3Reliability
If pipeline stall is used to clear hazards, then memory request failure is handled, but productivity decreases due to performance cost for all allocated threads
Solution Approach 1:
The patent segments the handling of memory requests into two independent paths: one for successful requests and one for failed requests. This segmentation ensures that failed requests are handled without affecting the performance of threads following the successful request path, thus maintaining productivity while ensuring reliability.
Solution Approach 2:
Instead of stalling the pipeline to clear hazards (the traditional approach), the patent inverts the approach by using the memory response path circuitry to actively reschedule threads with failed requests. This inversion allows hazard clearance without the performance penalty associated with pipeline stalls.
Data Source
AI summary
Devices and techniques to reschedule a memory request that has failed when a thread is executing in a processor are described herein. When a memory request for a thread is denied at a point in the execution pipeline of the processor beyond a thread rescheduling point, the thread can be placed into a memory response path of the processor. An indicator that a register write-back will not occur for the thread can also be provided. Then, the thread can be rescheduled with other threads in the memory response path.