Reservation Station Load Replay Preclusion
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Solution Overview
Problem
In out-of-order processors, the power wastage due to frequent load replays from non-core resources, such as fuse arrays and L2 caches, is significant, leading to increased power utilization and thermal issues, despite minimal performance impact, as these resources are shared among processor cores and access times are longer compared to on-core caches.
Innovation Solution
A power-saving mechanism is implemented by using reservation stations to detect specified load micro instructions directed to non-core resources and stall younger dependent micro instructions until the load is completed, reducing the number of replays and enabling power management in execution units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If load micro instructions are dispatched to execution units without detection of non-core resource accesses, then execution throughput is maintained, but power consumption increases due to frequent replays
Solution Approach 1:
The patent applies preliminary action by detecting load micro instructions destined for non-core resources before they are dispatched to execution units. The detection mechanism identifies these instructions in advance and prevents their dispatch, thereby avoiding the power consumption associated with subsequent replays while maintaining execution throughput for other instructions.
Solution Approach 2:
The patent introduces an intermediary detection mechanism between the instruction dispatch logic and execution units. This intermediary component monitors load micro instructions, identifies those accessing non-core resources, and intercepts them before dispatch. The intermediary enables the system to differentiate between cacheable and non-cacheable loads, preventing unnecessary dispatches and reducing power consumption without impacting overall execution throughput.
2Reliability
If younger dependent micro instructions are stalled until load completion, then replay frequency is reduced, but execution latency increases
Solution Approach 1:
The patent applies local quality by selectively stalling only those younger dependent micro instructions that are affected by non-core resource accesses, rather than stalling all instructions. The detection mechanism identifies specific load instructions and their dependent instructions, applying the stall condition locally to the affected instruction stream while allowing other independent instructions to proceed, thereby minimizing overall execution latency.
Solution Approach 2:
The patent uses preliminary action by detecting and stalling younger dependent instructions in advance before they are dispatched to execution units. By identifying the dependency relationship between load instructions and younger instructions beforehand, the system prevents unnecessary dispatches and subsequent replays, reducing the net execution time despite the stall condition.
3Use of energy by stationary object
If detection logic is added to identify specified load micro instructions, then power management is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the detection logic to serve multiple functions: identifying load micro instructions, determining their destination (core vs. non-core resources), and controlling dispatch decisions. This multi-functional approach consolidates what could be separate complex components into a single integrated detection mechanism, improving power management while limiting the increase in device complexity.
Solution Approach 2:
The patent uses parameter changes by modifying the dispatch condition based on the detected instruction type. The detection logic evaluates parameters of load micro instructions (such as memory access characteristics) and changes the dispatch parameter accordingly - allowing dispatch for cacheable loads and preventing dispatch for non-cacheable loads. This parameter-based control enables sophisticated power management with relatively simple detection logic.
Data Source
AI summary
An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a random access memory, programmed via a Joint Test Action Group interface with the plurality of specified load instructions corresponding to the out-of-order processor which, upon initialization, accesses the random access memory to determine said plurality of specified load instructions.