Reservation Station Queue Micro-Instruction Release Circuit

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Solution Overview

Problem

Current superscalar microprocessors face performance degradation due to cache misses, which require replaying arithmetic logic micro-instructions, leading to significant time consumption and reduced efficiency.

Innovation Solution

A method and apparatus for scheduling micro-instructions that detect load write-back signals and determine cache hit/miss status to trigger a release circuit, preventing unnecessary replay operations by removing micro-instructions from the reservation station queue when a cache hit is confirmed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the reservation station assumes a fixed delay for load micro-instruction execution, then the scheduling is simplified, but cache misses cause replay operations that reduce performance

Engineering Contradiction:

Improvescheduling complexityVSAvoidmicroprocessor performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent makes the reservation station queue dynamically adjustable by adding a release circuit that can selectively remove micro-instructions based on cache hit/miss detection. This transforms the static fixed-delay assumption into a dynamic system that adapts to actual cache performance, resolving the contradiction between scheduling simplicity and performance.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent implements a feedback mechanism where the load execution unit broadcasts write-back signals that are detected by detection logic. This feedback loop allows the system to know when data is actually ready, enabling the release circuit to make informed decisions about removing micro-instructions from the queue, thus improving performance without excessive complexity.

Inventive Principle:

Principle #23Feedback

2Speed

If arithmetic logic micro-instructions are dispatched early based on fixed delay assumption, then instruction throughput is improved, but cache misses cause execution failures requiring replay

Engineering Contradiction:

Improveinstruction throughputVSAvoidexecution correctness

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent performs preliminary detection of cache hit/miss status by monitoring load write-back signals before micro-instructions are executed. The detection logic prepares the release circuit in advance, so when data is actually ready (cache hit), the micro-instruction can be safely removed from the queue, preventing replay operations and ensuring execution correctness.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary release circuit between the reservation station queue and the execution units. This intermediary selectively removes micro-instructions based on cache status detection, acting as a mediator that ensures only correctly executable instructions are dispatched, thus maintaining reliability while preserving throughput.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If micro-instructions are retained in the reservation station queue, then replay operations are avoided, but queue occupancy increases potentially blocking new instructions

Engineering Contradiction:

Improveexecution correctnessVSAvoidqueue management complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts micro-instructions from the reservation station queue selectively based on cache hit detection. The release circuit removes only those micro-instructions whose source data is confirmed ready, preventing replay operations. This targeted extraction maintains execution correctness while minimizing queue occupancy impact.

Inventive Principle:

Principle #2Taking out (Extraction)

4Ease of manufacture

If the reservation station uses conventional fixed delay scheduling, then hardware design is simplified, but cache misses cause time loss due to replay operations

Engineering Contradiction:

Improvedesign simplicityVSAvoidreplay operation time

Core Design Contradiction:

Ease of manufactureVSLoss of time

Solution Approach 1:

The patent adds a feedback mechanism where load write-back signals are detected and used to control the release circuit. This feedback allows the system to distinguish between cache hits and misses, removing micro-instructions only when appropriate. The added complexity is minimal (detection logic and release circuit) but eliminates time loss from replay operations.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS10860327B2Methods for scheduling that determine whether to remove a dependent micro-instruction from a reservation station queue based on determining a cache hit/miss status of a load micro-instruction once a count reaches a predetermined value and an apparatus using the same

Publication Date: 2020.12.08 VIA ALLIANCE SEMICON CO LTD

AI summary

A method for scheduling micro-instructions, performed by a qualifier, is provided. The method includes the following steps: detecting a load write-back signal broadcasted by a load execution unit; determining whether to trigger a load-detection counting logic according to content of the load write-back signal; determining whether an execution status of a load micro-instruction is cache hit when the triggered load-detection counting logic reaches a predetermined value; and driving a release circuit to remove the first micro-instruction in a reservation station queue when the execution status of the load micro-instruction is cache hit and the first micro-instruction has been dispatched to an arithmetic and logic unit for execution.