Reserved Cache Line ECC for Device-Failure Memory Protection
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Solution Overview
Problem
Current reliability features in memory systems, such as rank sparing and double device data correction, are resource-inefficient due to high power consumption and reduced bandwidth, and are wasteful of system resources.
Innovation Solution
Reserving a cache line in a memory page for error correction, where the reserved cache line stores extra ECC bytes to enable single device data correction without performance or power costs, and is used only after a device failure to detect and correct errors, allowing for 100% detection and correction of a second device failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If rank sparing is used to cover for a failed device, then reliability is improved, but system resources are wasted due to holding a whole rank in reserve
Solution Approach 1:
The patent divides the error correction capability into segments: normal ECC bytes handle single-device errors, while reserved cache lines provide additional error correction capacity specifically for multi-device failure scenarios. This segmentation allows resources to be allocated only when needed, avoiding the waste of reserving entire ranks.
Solution Approach 2:
The patent pre-allocates reserved cache lines that are not visible to the memory system addressing mechanism during normal operation. These reserved lines are prepared in advance but only activated when device failures are detected, allowing the system to maintain high resource utilization during normal operation while having error correction capacity ready when needed.
2Reliability
If double device data correction (DDDC) is used, then reliability is improved, but power consumption increases and bandwidth is reduced due to lockstepping requirements
Solution Approach 1:
The patent implements a dynamic error correction system where the ECC mechanism adapts its operation based on detected failures. During normal operation, standard ECC provides single-device correction with minimal overhead. After device failures are detected, the system dynamically reconfigures to use reserved cache lines for enhanced error correction, avoiding continuous high-power operation while maintaining reliability when needed.
Solution Approach 2:
The patent changes the operational parameters of the ECC system based on system state. When no failures are detected, the system operates in normal mode with standard ECC bytes. When device failures are detected, the system transitions to a different operational mode where reserved cache lines are activated and additional ECC bytes are utilized, optimizing the balance between reliability and power consumption for each operational state.
3Reliability
If DDDC with lockstepping is implemented, then reliability is improved, but bandwidth is reduced
Solution Approach 1:
The patent segments the error correction functionality so that normal cache lines maintain their standard access patterns and bandwidth characteristics, while reserved cache lines provide supplementary error correction capacity. This segmentation allows the majority of memory operations to proceed at full bandwidth without the restrictions of lockstepping, while still providing enhanced reliability through the reserved lines.
Solution Approach 2:
The reserved cache lines act as intermediaries that provide error correction support without directly interfering with normal memory access operations. The system can detect errors in active cache lines and use the reserved lines to provide correction data without requiring lockstepped operation, thus maintaining bandwidth while improving reliability.
Data Source
AI summary
Methods, techniques, systems and apparatuses for utilizing reserved space for error correcting functionality. A cache line (“reserved line”) in a plurality of cache lines to store error correcting code (ECC) data is utilized for storing ECC data corresponding to other cache lines within the plurality of cache lines when a memory device has failed.