Reserved Cache Slots for Inclusive Memory Tracking
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Solution Overview
Problem
In computing systems with multi-level system memory, the inefficiency in cache line management between near memory and far memory leads to violations of inclusive tracking modes, resulting in unnecessary read operations and increased traffic, especially in multi-processor systems.
Innovation Solution
Implementing a system where cache home agents (CHAs) track the inclusive/non-inclusive states of cache lines, allowing direct writes to near memory without prior reads for cache lines in inclusive states, and ensuring all memory requests pass through a CHA logic unit for comprehensive tracking, along with reserving cache slots for Memory Encryption Engine (MEE) meta-data to handle non-inclusive treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache lines are managed without tracking inclusive/non-inclusive states, then the system memory operations are simpler, but unnecessary read operations occur and traffic increases
Solution Approach 1:
The patent applies preliminary action by pre-tracking the inclusive/non-inclusive states of cache lines before write operations occur. The CHA logic unit maintains state information that determines whether a cache line has an inclusive copy in near memory, allowing the system to proactively decide whether to perform read operations before writes, thereby avoiding unnecessary traffic.
Solution Approach 2:
The CHA logic unit serves as an intermediary between the processor and the memory system. It introduces state tracking mechanisms that mediate between cache line management and memory operations, determining whether inclusive mode guarantees apply and whether read operations are necessary before writes to near memory.
2Reliability
If all memory requests pass through CHA logic unit for tracking, then inclusive mode guarantees are maintained, but the processing path becomes longer
Solution Approach 1:
The patent applies local quality by implementing state tracking only for cache lines that require inclusive mode guarantees. The CHA logic unit maintains state information selectively for cache lines that map to near memory, allowing differentiated handling where only specific memory requests undergo additional tracking checks rather than all requests uniformly.
3Reliability
If cache slots are reserved for MEE meta-data, then non-inclusive treatment is properly handled, but available cache capacity for regular data is reduced
Solution Approach 1:
The patent applies segmentation by dividing the near memory cache into distinct segments: regular cache slots for general data and specially reserved cache slots for MEE meta-data. This segmentation allows the system to properly handle non-inclusive treatment for encryption-related operations while maintaining adequate capacity for regular computing operations.
Data Source
AI summary
Electronic circuitry of a computing system is described where the computing system includes a multi-level system memory where the multi-level system memory includes a near memory cache. The computing system directs system memory access requests whose addresses map to a same near memory cache slot to a same home caching agent so that the same home caching agent can characterize individual cache lines as inclusive or non-inclusive before forwarding the requests to a system memory controller, and where the computing system directs other system memory access requests to the system memory controller without passing the other requests through a home caching agent. The electronic circuitry is to modify the respective original addresses of the other requests to include a special code that causes the other system memory access requests to map to a specific pre-determined set of slots within the near memory cache.