Reserved Memory Cells for Defect Position Error Correction
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Solution Overview
Problem
Non-volatile memory systems face challenges in identifying and managing defective data storage cells, which can lead to distorted information and reduced reliability due to manufacturing errors or wear and tear, limiting the effectiveness of error correction mechanisms.
Innovation Solution
The use of reserved or 'pilot' cells to identify and mark defective data storage cells, allowing for the exclusion of defective cell data during read and write operations, thereby enhancing error correction capabilities without requiring additional circuitry or resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error correction codes and defect management schemes are used to recover information from defective cells, then data reliability is improved, but device complexity and processing overhead increase
Solution Approach 1:
The patent applies preliminary action by pre-marking defective cell positions during manufacturing or initial characterization, storing this defect map in reserved cells before normal data operations begin. This allows the system to proactively avoid defective cells rather than reacting to errors during read/write operations, reducing the complexity of real-time error correction processing.
Solution Approach 2:
The patent extracts defective cell position information from the main data storage functionality and separates it into dedicated reserved cells. By taking out the defect management function from regular data cells and placing it in specialized reserved cells, the system simplifies the overall processing overhead while maintaining reliability.
2Reliability
If reserved cells are used to store defect position information, then error correction capability is improved, but storage capacity is reduced
Solution Approach 1:
The patent applies multi-functionality by designing reserved cells that serve dual purposes: they provide reference voltages/currents for multi-bit data storage operations and simultaneously store defect position information. This universal use of reserved cells maximizes their utility while minimizing the impact on overall storage capacity.
Solution Approach 2:
The patent changes the functional parameter of reserved cells from solely providing reference signals to also encoding defect position information. By modifying what parameters these cells store (from only voltage reference levels to including defect status bits), the system achieves improved error correction without requiring additional dedicated defect storage cells.
3Reliability
If defective cells are identified and avoided, then data distortion is reduced, but manufacturing yield and cell utilization decrease
Solution Approach 1:
The patent applies local quality by allowing different regions of the memory array to have different functional characteristics. Cells identified as defective are locally marked in reserved cells, enabling the system to maintain high utilization of good cells while isolating and avoiding only the specific defective locations, rather than reducing overall array utilization.
Solution Approach 2:
The patent uses reserved cells as copies or proxies that store defect position information without affecting the actual data storage function of the main array. By copying defect status into these reference cells, the system can track and avoid defective cells while maintaining full utilization of the primary storage array.
Data Source
AI summary
A circuit including a memory and an error correction code circuit. The memory including (i) a plurality of data storage cells and (ii) at least one reserved cell configured to store status information identifying a status of one or more of the plurality of data storage cells. Each of the data storage cells is configured to store a plurality of data bits. Each of the at least one reserved cell includes a multi-bit cell configured to store a lower density of information than each of the data storage cells. The error correction code circuit is configured to indicate, in a data stream formed from the memory, positions of data from the data storage cells for which status information is stored.


