Reserved Memory Pages for Multi-Page Address Translation
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Solution Overview
Problem
The increasing storage capacity of non-volatile memory devices, such as SSDs, requires larger amounts of volatile memory like DRAM for fast performance, leading to increased size, power consumption, and manufacturing costs, while existing techniques for reducing DRAM size, such as L2P table swapping and large translation units, result in higher latency and wear out the memory device.
Innovation Solution
Implementing dynamic reservation and unreservation of memory pages to form multi-page translation units, allowing efficient read and write address translation by excluding or including memory pages, thereby reducing the size of the L2P table and DRAM requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If larger amounts of volatile memory (DRAM) are used to support increasing storage capacity of non-volatile memory devices, then fast performance and address translation capability are improved, but physical footprint, power consumption, and manufacturing costs increase
Solution Approach 1:
The patent segments the DRAM resource allocation by implementing dynamic reservation and unreservation of memory pages. Instead of allocating fixed large DRAM capacity, the system divides DRAM into reserved pages for L2P tables and unreserved pages that can be dynamically allocated, enabling fine-grained control over memory usage and reducing overall DRAM requirements while maintaining translation capability.
Solution Approach 2:
The patent applies dynamics by implementing dynamic reservation and unreservation of memory pages based on workload demands. The system can adjust the amount of DRAM allocated for L2P tables in real-time, expanding when translation demand is high and contracting when demand is low, thereby optimizing the balance between performance and power consumption.
2Speed
If larger amounts of volatile memory (DRAM) are used to support increasing storage capacity, then address translation speed is improved, but physical footprint and manufacturing costs increase
Solution Approach 1:
The patent segments DRAM usage into reserved and unreserved pages, allowing the system to maintain sufficient translation speed by ensuring reserved pages are always available for L2P operations while minimizing total DRAM footprint through dynamic unreservation of unused pages.
Solution Approach 2:
The patent changes the parameter of DRAM allocation from static to dynamic by implementing reservation and unreservation mechanisms. This allows the system to optimize the balance between translation speed (requiring sufficient DRAM) and physical footprint (requiring minimal DRAM) by adjusting allocation parameters based on actual workload conditions.
3Quantity of substance
If L2P table swapping technique is used to reduce DRAM size, then DRAM requirements are reduced, but latency increases and memory device wear out accelerates
Solution Approach 1:
The patent applies preliminary action by pre-reserving memory pages for L2P table storage before they are needed. This ensures that when address translation is required, the reserved pages are immediately available, eliminating the latency associated with swapping operations while still reducing overall DRAM requirements through dynamic unreservation when not in use.
4Quantity of substance
If large translation units are used to reduce DRAM size, then DRAM requirements are reduced, but latency increases and memory device wear out accelerates
Solution Approach 1:
The patent segments the translation process by using reserved memory pages that can accommodate translation units of appropriate size without forcing excessively large translation units. This segmentation allows the system to reduce DRAM requirements through dynamic allocation while avoiding the reliability issues caused by overly large translation units that would increase wear.
Data Source
AI summary
In some implementations, a memory device may receive a write command that includes data to be written to multiple memory pages of a translation unit (TU) of the memory device. The multiple memory pages of the TU may span multiple memory planes of the memory device. The memory device may identify the multiple memory pages of the TU, to which the data is to be written, based on one or more bad blocks of the memory device and a determination of whether one or more memory pages of the memory device are to be reserved. The memory device may write the data to the multiple memory pages of the TU.