Reset Circuit Error Logging for Fatal System Reboots
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Solution Overview
Problem
Global fatal error events in computer systems often result in reboots without executing error-handling code, preventing effective error logging and diagnosis, which hampers error detection and containment capabilities.
Innovation Solution
A reset circuit is configured to reestablish communication pathways between the main processor and downstream devices, allowing the management processor to write to cleared registers and execute error-handling code to generate an error log after a fatal error, ensuring that error logs are created even during system reboots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system reboots immediately upon detecting a global fatal error, then system stability is maintained, but error logging capability is lost
Solution Approach 1:
The patent applies preliminary action by having the reset circuit assert the reset signal immediately upon detecting a fatal error, before the processor can execute error-handling code. This ensures the system reboots to a stable state while the error condition is captured in the error register, preserving error information for later analysis without requiring the processor to complete its current execution cycle.
Solution Approach 2:
The patent introduces an intermediary error register that captures and holds error information independently of the processor's execution state. The reset circuit writes the error condition to this register before resetting the processor, allowing the error information to be preserved and retrieved after reboot without requiring the processor to remain in its pre-error state.
2Loss of information
If error-handling code is executed before reboot, then error logging is enabled, but system reboot is delayed
Solution Approach 1:
The patent performs the critical error capture action preliminarily by having the reset circuit write the error condition to the error register immediately upon detection, before the processor has a chance to execute any error-handling code. This preliminary capture of error information eliminates the need to wait for processor execution, thereby avoiding reboot delay while ensuring error logging is enabled.
3Speed
If the reset circuit asserts reset signal immediately, then system reboot is fast, but error-handling code cannot execute
Solution Approach 1:
The patent uses an intermediary error register as a buffer between the reset circuit and the processor. The reset circuit can assert the reset signal immediately to achieve fast reboot, while simultaneously writing the error condition to the intermediary register. This intermediary structure allows the reset to proceed without waiting for processor execution, yet error information is preserved for later retrieval.
Solution Approach 2:
The reset circuit performs preliminary capture of the error condition by writing to the error register before asserting the reset signal. This preliminary action ensures error information is preserved even though the processor will not have a chance to execute error-handling code during the immediate reboot sequence.
Data Source
AI summary
Method and system of error logging. At least some of the illustrative embodiments are methods including detecting assertion of an error pin by a processor system, (comprising at least a main processor and a chipset, the assertion of the error pin an indication to reboot the processor system) the detecting by a reset circuit, notifying a management processor (distinct from the main processor) that the error pin is asserted (the notifying by the reset circuit), writing to a plurality of registers in the chipset (the writing by the management processor), de-asserting a reset pin of the main processor, and then executing by the main processor an error-handling code to generate an error log.