Synchronous Reset Circuit Fault Detection With Cascaded Flip-Flops
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Solution Overview
Problem
Faults in synchronous reset signal generation circuits can lead to resetting failures, posing serious risks in systems that require high reliability, such as vehicle-mounted and industrial equipment, necessitating a technology for effective fault detection and determination.
Innovation Solution
A synchronous reset signal generation circuit is designed with multiple flip-flops in cascade arrangements to generate synchronous reset signals, error determination signals, and a fault determination circuit that assesses the presence of faults based on these signals, ensuring reliable synchronization reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous reset signal generation circuit is used to ensure stable initialization of logic circuits, then system reliability is improved, but the risk of resetting failures due to faults in the circuit increases without proper detection mechanisms
Solution Approach 1:
The patent implements preliminary fault detection by generating error determination signals E1 and E2 before the synchronous reset signal SRSTN is fully generated. These error signals are produced by parallel cascaded flip-flop circuits that monitor the generation process in advance, allowing the system to detect potential faults before they cause resetting failures, thus resolving the contradiction between maintaining reliability and preventing harmful effects.
Solution Approach 2:
The patent establishes a feedback mechanism where the fault determination circuit continuously monitors the synchronous reset signal generation process by comparing error determination signals E1 and E2. When a fault is detected through this feedback loop, the system can identify resetting failure risks and take appropriate actions, thereby maintaining system reliability while preventing harmful resetting failures.
2Difficulty of detecting and measuring
If multiple flip-flops are added to generate error determination signals for fault detection, then fault detection capability is improved, but circuit complexity increases
Solution Approach 1:
The patent segments the fault detection function into two independent parallel cascaded flip-flop circuits, each generating error determination signals E1 and E2 separately. This segmentation allows the complex fault detection task to be divided into simpler sub-tasks that can be implemented using standard flip-flop components, improving detectability while managing circuit complexity through modular design.
Solution Approach 2:
The patent uses copying by creating parallel copies of the cascaded flip-flop structure to generate error determination signals. Instead of using a single complex detection circuit, multiple simplified copy circuits are employed that perform the same detection function independently, thereby improving fault detection capability while keeping each individual circuit segment simple and manageable.
3Measurement precision
If error determination signals are generated through parallel cascaded flip-flop circuits, then fault detection accuracy is improved, but the number of components and circuit complexity increase
Solution Approach 1:
The patent applies partial action by using two parallel cascaded flip-flop circuits that generate error determination signals at different stages of the synchronous reset signal generation process. This partial monitoring approach provides sufficient fault detection accuracy for critical errors without requiring complete monitoring of every signal transition, thereby achieving acceptable detection precision with a manageable number of flip-flop components.
Data Source
AI summary
A synchronous reset signal is generated from an asynchronous reset signal. The synchronous reset signal is output from the final-stage FF among L FFs connected in a cascade arrangement. A first error determination signal is output from the final-stage FF among M FFs connected in a cascade arrangement. Among N FFs connected in a cascade arrangement, the initial-stage FF receives the first error determination signal, and the final-stage FF outputs a second error determination signal. Based on the three outputs, the presence or absence of a fault in the circuit is determined. L, M, and N fulfil M≥2, L≥M+1, and M+N≥L+1.