Power-On Reset Circuit With Feedback Latch for Jitter Stability
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Solution Overview
Problem
Traditional power on reset circuits in wireless charging control chips face instability and jitter issues due to input voltage fluctuations, leading to abnormal behavior in other circuit modules and difficulties in adjusting the power on reset time without increasing chip area or altering layout.
Innovation Solution
A power on reset circuit with a bias current generation module, a power on reset module featuring two series switches to adjust charging current, and a feedback latch module with a feedback branch formed by NMOS transistors to stabilize the power on reset signal and prevent jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If traditional power on reset circuits use PMOS to charge capacitors and output after several stages of inverters, then the power on reset time can be prolonged, but the power on reset output signal becomes unstable and may jump, causing abnormities in other circuit modules
Solution Approach 1:
The patent introduces a feedback mechanism where the output signal of the inverter chain is fed back to the input through a feedback network. This feedback stabilizes the output signal by correcting deviations caused by power voltage jitter, preventing signal jumps while maintaining the prolonged reset time achieved through PMOS charging of capacitors.
Solution Approach 2:
The patent uses capacitors charged by PMOS transistors to store energy beforehand, creating a cushion that maintains stable operation during the power-on transition period. This pre-charging mechanism ensures that the circuit has sufficient energy reserves to withstand voltage fluctuations, thereby preventing signal instability while achieving the desired reset duration.
2Duration of action of moving object
If the width to length ratio of charging PMOS transistors is decreased or capacitor area is increased to prolong power on reset time, then the reset time is extended, but the chip area is increased and layout is changed
Solution Approach 1:
The patent achieves adjustment of power-on reset time by changing the parameters (width-to-length ratio) of the PMOS transistors in the feedback network rather than increasing capacitor areas. This parameter modification allows precise control of charging current and reset duration without proportionally increasing chip area, as the feedback mechanism amplifies the effect of smaller transistor changes.
Solution Approach 2:
The PMOS transistors in the patent serve multiple functions: they charge the capacitors to establish the reset duration and simultaneously participate in the feedback mechanism to stabilize the output signal. This multi-functionality eliminates the need for separate components that would otherwise be required, thereby extending reset time without proportional increases in chip area.
3Reliability
If power voltage jitters within the input voltage range VIL-VIH of the inverters in the power on stage, then the power on reset output signal jumps, but using traditional circuit structures cannot effectively restrain this jitter
Solution Approach 1:
The patent employs a feedback loop that continuously monitors the output signal and adjusts the input to the inverter chain accordingly. When power voltage jitter causes the output to approach the transition threshold (VIL-VIH range), the feedback mechanism counteracts these variations, effectively restraining jitter and preventing signal jumps without requiring changes to the inverter characteristics.
Data Source
AI summary
A power on reset circuit includes a bias current generation module for generating a bias current, a power on reset module for generating a power on reset voltage signal, and a feedback latch module, which are electrically connected in sequence. The power on reset module includes two series switches capable of being turned on or off to adjust the bias current to further adjust the power on reset time. The feedback latch module is used for latching the power on reset voltage signal to restrain the jitter of the power voltage within the input voltage range VIL-VIH of inverters in the power on stage and to avoid jump of the signal. The feedback latch module comprises a feedback branch, which is formed by two NMOS transistors in series connection and achieves rapider and stable output of the power on reset voltage signal through feedback of the signal.