Reset Management Circuit for Uninterrupted IC Testing
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Solution Overview
Problem
Complex integrated circuits face challenges in managing reset signals during testing, particularly when multiple reset sources are involved, which can disrupt test operations and complicate the determination of operational margins.
Innovation Solution
An integrated circuit with reset management circuitry that selectively blocks or delays reset indications during testing, using flip-flops and logic gates to manage reset signals based on test mode enable signals, allowing tests to complete without interruption and ensuring proper reset timing post-test.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reset management circuitry blocks reset indications during test operations, then test continuity is improved, but reset protection functionality is temporarily suspended
Solution Approach 1:
The reset management circuitry dynamically switches between blocking and non-blocking modes based on the test operation state. When a test operation is detected, the circuitry blocks reset indications to ensure test continuity. When no test operation is active, the circuitry allows reset indications to pass through to maintain system protection. This dynamic adaptation resolves the contradiction between test continuity and reset protection.
Solution Approach 2:
The reset management circuitry acts as an intermediary between the reset indication source and the rest of the system. It receives reset indications, evaluates whether a test operation is currently active, and selectively passes or blocks the reset indication based on this evaluation. This intermediary function allows the system to maintain both test continuity and reset protection by controlling the flow of reset signals at the appropriate moment.
2Reliability
If multiple reset sources are monitored, then system reliability is improved, but circuit complexity increases
Solution Approach 1:
The reset management circuitry merges the monitoring of multiple reset sources into a single unified evaluation process. Instead of handling each reset source independently with separate logic circuits, the design combines all reset indications into a common evaluation point where a single test operation status check determines whether to block or pass any active reset indication. This merging approach maintains comprehensive monitoring of multiple reset sources while significantly reducing the overall circuit complexity.
Data Source
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AI summary
A signal management circuit includes a first input terminal to receive a first signal. A first logic portion is coupled to the first input terminal and configured to provide a first output signal. A second logic portion is coupled to receive a second signal and configured to provide a second output signal. The second signal is based on the first output signal and the first signal. An output terminal is coupled to provide a third output signal based on the first output signal and the second output signal.