Reset Circuit for Self-Timed Compiler Memory Cycle Termination
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Solution Overview
Problem
Self-timed compiler memories face limitations in cycle time due to the slower precharging of dummy bitlines compared to bitlines, which restricts the memory device's overall speed and efficiency.
Innovation Solution
A novel technique involving a tracking circuit with a dummy bitline and dummy wordline that generates a reset signal upon specific conditions, allowing for synchronized precharging of both bitlines and dummy bitlines, thereby resetting the internal clock and enabling efficient precharging of bitlines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the discharge transistor size for DBL is increased to match BL discharge speed, then DBL discharges faster, but the area of the memory device increases
Solution Approach 1:
The patent applies different transistor sizes for different components: small transistors for memory cell bitlines (BL) to minimize area, and larger transistors for dummy bitline (DBL) discharge path to achieve fast discharge. This local differentiation of component dimensions resolves the contradiction between fast DBL discharge and small memory area.
2Reliability
If DBL is precharged back to logic high for the next read cycle, then DBL is ready for next cycle, but the precharge time significantly exceeds BL precharge time
Solution Approach 1:
The patent introduces a preliminary discharge phase where DBL is discharged to a intermediate voltage level (not fully to logic low) before the main read operation. This preliminary action prepares DBL for faster subsequent precharging while maintaining the reliability of the read cycle timing.
3Measurement precision
If BLs are discharged to logic low completely, then sensing is accurate, but the precharge time for next cycle is extended
Solution Approach 1:
The patent applies partial discharge to BLs, discharging them only to a small extent (about 100 millivolts) rather than completely to logic low. This partial action is sufficient for accurate sensing through the sense amplifier while significantly reducing the precharge time required for the next cycle, resolving the contradiction between sensing accuracy and precharge speed.
Data Source
AI summary
A method and circuit for termination of internal cycle and its associated tracking circuits in high performance self timed compiler memories is disclosed. In one embodiment, a method of timing the precharging of BLs in a self timed compiler memory array includes initiating an internal clock during the start of a read/write cycle by a control block, triggering DWL and WLs to go high upon initiating the internal clock by the control block, triggering DBL and BLs to go low upon the DWL and WLs going high by the control block, generating a reset BL signal upon the DWL going high and the DBL going low by the tracking circuit, disabling the DBL from going further low upon receiving the reset BL signal by the tracking circuit, and precharging the DBL to go high upon receiving the reset BL signal by the precharge circuit.