Reset Circuit Timing for Stable Power-On Detection
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Solution Overview
Problem
Existing reset circuits in semiconductor devices face challenges in generating reliable reset signals during power-on and power-down due to issues with voltage division, transistor balance, and capacitor degradation, leading to malfunction and reduced device lifespan.
Innovation Solution
A reset circuit design incorporating power-on and power-down detection circuits with clamping switches and leak prevention mechanisms, along with a starter circuit that prevents capacitor degradation by disconnecting the capacitor from the power supply during the power hold period, ensuring accurate signal generation and extended device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is used in the starter circuit to initialize the detection circuit at power-on, then the detection circuit can be properly initialized, but the capacitor degrades due to TDDB (Time-Dependent Dielectric-Breakdown) and may cause reliability failure
Solution Approach 1:
The patent extracts the harmful continuous voltage application from the capacitor by introducing a switch that disconnects the capacitor from the power supply during the power hold period. This separates the initialization function (when capacitor is connected) from the steady-state operation (when capacitor is disconnected), preventing TDDB degradation while maintaining proper circuit initialization.
Solution Approach 2:
The patent implements periodic connection and disconnection of the capacitor through a switch controlled by detection circuits. The capacitor is connected only during power-on initialization and disconnected during power hold period, creating a periodic action pattern that eliminates continuous stress and prevents degradation.
2Reliability
If the power supply voltage increases slowly or swings at power-on, then the dividing circuit cannot output a normal voltage, but the drain node changes to ground voltage by the transistor being turned on, causing the power-on detection signal to fail
Solution Approach 1:
The patent applies preliminary action by using the starter circuit to force-initialize the detection circuit at power-on before normal voltage division begins. This preliminary initialization ensures the detection circuit is in a known state even when voltage increases slowly or swings, preventing false detection and ensuring reliable power-on signal generation.
Solution Approach 2:
The patent introduces a switch as an intermediary between the power supply and the detection circuit. This switch mediates the connection during critical power-on transitions, allowing controlled initialization while protecting against abnormal voltage conditions that would otherwise cause incorrect detection.
3Use of energy by moving object
If the load circuit is constituted of a pMOS transistor with small drivability, then the circuit achieves low power consumption, but the drain node changes to ground voltage when the transistor is slightly turned on
Solution Approach 1:
The patent applies preliminary anti-action by using the starter circuit to preemptively set the drain node to a known state before the load circuit transistor can cause voltage instability. This preliminary action counteracts the potential harmful effect of the transistor turning on during slow voltage rise, ensuring the drain node remains stable.
Data Source
AI summary
In a power-on detection circuit, a first connection node at which a first divided voltage is generated is connected to a second power supply line during activation of a power-down detection signal. Inactivation timing of the power-down detection signal is set earlier than an activation timing of a power-on detection signal. Therefore, the first transistor whose gate is connected to the first connection node is certainly turned off in the first half of a power-on period, which prevents the power-on detection signal from being activated during the power-on period. Further, a leak current flowing through the first transistor is reduced. In the second half of the power-on period, the power-on detection signal is certainly generated using the first divided voltage generated by the first dividing circuit. Thus, operating a reset circuit without malfunction and normally outputting a reset signal is possible disregarding behavior of a power supply voltage at power-on.