Reset Circuit Assembly With RC Delay for Device Readiness

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Solution Overview

Problem

Conventional reset circuits in computer systems are complex and costly, and they do not account for the delay in starting devices simultaneously, which can lead to incorrect signals and accidents due to unready devices during the reset process.

Innovation Solution

A hard reset and manual reset circuit assembly with a simple and low-cost design, utilizing resistors, capacitors, and semiconductor switches to provide a delay in the reset process, ensuring external devices have sufficient time to reach a ready status, comprising a power source, resistors, capacitors, and semiconductor switches connected in a specific configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional reset circuits use switching mode power supply and power-on signal generator, then the reset function can be provided, but the circuit structure becomes complicated and manufacturing cost increases

Engineering Contradiction:
Improvereset functionVSAvoidcircuit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the complex switching mode power supply and power-on signal generator from the reset circuit, retaining only the essential reset functionality through a simplified RC circuit with transistor switches. This eliminates unnecessary components while preserving the core reset function.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces expensive, complex power supply components with inexpensive, simple RC circuit elements (resistors, capacitors, and transistors) that can be easily manufactured and replaced. The simplified circuit uses basic, low-cost components to achieve the same reset function.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Speed

If all devices start simultaneously during reset, then the reset process is fast, but incorrect signals may be produced due to unready devices

Engineering Contradiction:
Improvereset speedVSAvoidsignal correctness
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements preliminary action by using the RC circuit to generate a delayed reset signal that waits for external devices to reach ready status before activating the reset function. The capacitor charges through the resistor, creating a time delay that ensures devices are prepared before reset occurs.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary RC circuit between the power source and the reset terminal, which mediates the timing between power availability and reset execution. This intermediary circuit ensures proper sequencing by delaying the reset signal until external devices are ready.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If delay is added to reset process for device readiness, then signal correctness is improved, but reset time increases

Engineering Contradiction:
Improvesignal correctnessVSAvoidreset time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent optimizes the delay parameters by carefully selecting resistor and capacitor values to achieve the minimum necessary delay for device readiness. By adjusting these parameters, the circuit provides just enough delay to ensure signal correctness while minimizing the time loss during reset.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The circuit design provides an effective reset function with a delay, allowing connected devices sufficient time to become ready, while reducing manufacturing costs through a simplified and inexpensive component layout.

Implementation Method 1

a first capacitor, the first capacitor comprising two opposite ends respectively connected to the control end of the second electric control switch and the grounding terminal

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS7616031B2Hard reset and manual reset circuit assembly
Publication Date: 2009.11.10 UNIVERSAL SCIENTIFIC INDUSTRIAL (SHANGHAI) CO LTD
  • US7616031B2 patent drawing
  • US7616031B2 patent drawing

AI summary

A simple inexpensive hard reset and manual reset circuit assembly that provides a delay time during reset for enabling other matched electronic devices to have sufficient time to reach ready status. The circuit assembly includes a power source, a first resistor, a first electric control switch, which has a control end and two bypasses being respectively connected to a reset terminal and a grounding terminal, a second resistor, a second electric control switch, which has a control end and two bypasses being respectively connected to the control end of the first electric control switch and the grounding terminal, a third resistor, a first capacitor, a second capacitor, a manual switch, which has two opposite ends respectively connected to the second capacitor and the grounding terminal, and a fourth resistor, which has two opposite ends respectively connected to the power source and the second end of the second capacitor.