Reset Circuit Self-Test for Multi-Source Reset Reliability
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Solution Overview
Problem
The challenge in complex processing systems, such as micro-controllers, is ensuring proper and timely reset operations to maintain a safe state, particularly in safety-critical applications like automotive systems, to comply with standards like ISO26262, where missed resets can be catastrophic.
Innovation Solution
A processing system with a reset circuit that combines and manages multiple reset-request signals, includes a test circuit for verifying the correct operation of the reset circuit, and performs a built-in self-test to ensure proper reset signal generation and connectivity, using combinational logic and masking/synchronization circuits to manage and validate reset signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the processing system increases in complexity to provide more functionalities and calculation power, then the processing capability and features are improved, but the difficulty of ensuring proper reset operations and maintaining safe state increases
Solution Approach 1:
The patent implements a feedback mechanism where the test circuit continuously monitors the reset circuit's operation and provides test results back to verify correctness. The built-in self-test functionality checks whether reset requests are properly generated and propagated, creating a closed-loop verification system that ensures reset reliability despite increasing system complexity
Solution Approach 2:
The processing system performs self-verification through built-in self-test functionality. The test circuit is integrated within the system and automatically tests the reset circuit without requiring external testing equipment, enabling the system to self-validate its safety-critical reset operations
2Reliability
If a test circuit is added to verify reset circuit operation, then the reliability of reset operations is improved, but the device complexity increases
Solution Approach 1:
The test circuit is merged with the existing reset circuit architecture. The test functionality is integrated into the same circuit structure, sharing common components and signal paths where possible, thereby reducing the overall complexity increase that would result from completely separate testing infrastructure
Solution Approach 2:
The test circuit is designed with multi-functionality, serving both as part of the normal reset operation pathway and as a verification mechanism. The same circuit elements are used for both operational reset functions and test/verification purposes, maximizing the utility of added components
Data Source
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AI summary
A processing system (10a) is described. The processing system comprises a reset circuit (116a) receiving a reset-request signal (RT'115) provided by a power-supply monitoring circuit (115) and further reset-request signals (RT'102, RT'120, RT'RP) provided by a microprocessor (1020, one or more further circuits (106, 110, 120) and/or a terminal (RP) of the processing system (10a). The reset circuit (116a) generates a combined reset-request signal (CRT) by combining (1162, 1166) the reset-request signals (RT'115, RT'102, RT'120, RT'RP). In response to the combined reset-request signal (CRT), the processing system (10a) is configured (116a, 118) to execute various phases in sequence. Specifically, in a reset phase, the reset circuit (116a) executes a reset of the processing system (10a). In a diagnostic phase, a diagnostic circuit (118) executes one or more tests of the processing system (10a). In a software runtime phase, the microprocessor (1020) is started. A hardware test circuit (40, 420, 422) is configured to repeat various operations during the diagnostic phase for each of the further reset-request signals (RT'102, RT'120, RT'RP). Specifically, the test circuit (40) masks (1004) the combined reset-request signal (CRT), asserts the respective further reset-request signal (RT'102, RT'120, RT'RP) and de-asserts all other further reset-request signals (RT'102, RT'120, RT'RP). Next, in response to determining that the combined reset-request signal (CRT) is de-asserted, the test circuit (40) generates a signal (STATE) indicating a failure of said reset circuit (116a).