Power-On Reset Circuit Topology to Prevent Through Current
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Solution Overview
Problem
Conventional power-on reset circuits experience instability in the reset signal during the rising edge of the source voltage, leading to through current flow from VDD to GND, potentially causing operational failures due to aged deterioration.
Innovation Solution
A power-on reset circuit for semiconductor integrated circuits that includes a determination unit with PMOS and NMOS transistors, where the conducting states of these transistors are controlled by monitoring signals to prevent simultaneous turn-on and thus avoid through current, featuring a first PMOS connected between VDD and a node, and second and third PMOS transistors in series, with NMOS transistors connected between the node and GND, ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power-on reset circuit uses a conventional design with monitoring units for both VDD and REG voltages, then the reset function can be provided for both voltage domains, but the reset signal becomes unstable during the rising edge period of REG, causing through current to flow from VDD to GND
Solution Approach 1:
The patent introduces a level shifter circuit as an intermediary component between the REG-voltage domain monitoring unit and the VDD-voltage domain output stage. This level shifter converts the reset signal from REG voltage level to VDD voltage level, ensuring stable signal transmission during voltage transitions and preventing the simultaneous turn-on of complementary transistors that would cause through current.
Solution Approach 2:
The patent implements a timing control mechanism where the reset signal generation is preliminary coordinated between the two monitoring units. The circuit ensures that the reset signal from the REG monitoring unit is properly timed and leveled before being combined with the VDD monitoring signal, preventing instability during the critical rising edge period of REG voltage.
2Adaptability or versatility
If the circuit monitors both VDD and REG voltages simultaneously, then comprehensive power-on detection is achieved, but the reset signal level becomes unstable during REG voltage rise-up period
Solution Approach 1:
The level shifter acts as a mediator that translates the reset signal from the REG voltage domain to the VDD voltage domain. This intermediary conversion ensures that the reset signal maintains proper voltage levels and stability throughout the entire power-on sequence, including the critical period when REG voltage is rising, thereby enabling stable dual-voltage monitoring.
Solution Approach 2:
The patent segments the power-on reset function into distinct voltage domains: a VDD monitoring unit operating at VDD level, a level shifter for voltage domain conversion, and a REG monitoring unit operating at REG level. This segmentation allows each component to operate optimally within its own voltage domain while maintaining overall system stability.
3Ease of operation
If the reset signal level becomes unstable during REG rising edge, then the PMOS and NMOS transistors may turn on simultaneously, but this creates through current path from VDD to GND
Solution Approach 1:
The level shifter serves as a protective intermediary that ensures proper voltage level translation and timing coordination between the monitoring units and the output stage. By maintaining stable voltage levels during the critical transition period, it prevents the simultaneous turn-on of PMOS and NMOS transistors, thereby eliminating the through current path while preserving the necessary transistor switching function.
Data Source
AI summary
A determination unit of a power-on reset circuit of a semiconductor integrated circuit is provided that ANDs (1) a first monitoring signal output from a first monitoring unit for monitoring when a first source voltage supplied from outside the semiconductor integrated circuit reaches a predetermined level and (2) a second monitoring signal output from a second monitoring unit for monitoring when an internal source voltage reaches a predetermined level, to produce a reset signal. In the determination unit, a first PMOS is inserted in series with a second PMOS connected between the first source voltage and a node. The conducting state of the second PMOS is controlled by the second monitoring signal. The conducting state of the first PMOS is controlled by the reset signal. Thus, even when the second monitoring signal becomes unstable and the second PMOS and a first NMOS are simultaneously turned on, the first PMOS is turned off, thus causing no flow of through current.