Reset Circuitry With Clock Gating for Meta-Stability Control
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Solution Overview
Problem
Complex reset architectures in integrated circuits lead to issues like reset domain crossings and asynchronous reset de-assertion, causing meta-stability and functional failures due to differing reset propagation delays across the circuit.
Innovation Solution
The implementation of a reset circuitry that includes a reset gating module and clock gating module, which generates clock gating instructions to synchronize reset signal propagation, ensuring that clocks are gated and re-instated based on pre-set time periods to prevent meta-stability and ensure consistent reset across all domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If asynchronous reset is used to avoid clock gating issues, then reset can be asserted independently of clock state, but meta-stability occurs in sequential elements with different reset sources
Solution Approach 1:
A reset management unit is introduced as an intermediary between the reset source and sequential elements. This unit receives the reset assertion independently of the clock state and manages the reset propagation to ensure all sequential elements are properly reset before clock operation resumes, preventing meta-stability while maintaining assertion independence.
Solution Approach 2:
The reset management unit performs preliminary actions by asserting reset to all sequential elements before clock gating is removed. This ensures that all sequential elements are in a known state before resuming operation, preventing meta-stability conditions while allowing independent reset assertion.
2Use of energy by moving object
If clock is gated to save power during reset, then power consumption is reduced, but reset de-assertion timing becomes critical to avoid meta-stability
Solution Approach 1:
The reset management unit implements feedback by monitoring the reset assertion signal and coordinating with the clock gating mechanism. When reset is asserted, the unit ensures clock gating remains active until reset is fully de-asserted across all sequential elements. This feedback loop eliminates the need for critical timing margins while maintaining power savings during reset operations.
3Reliability
If reset propagation delay varies across different device locations, then remote sequential elements may miss clock edges, but increasing reset signal strength does not uniformly reduce propagation delay
Solution Approach 1:
The reset management unit performs preliminary action by extending the reset assertion duration to account for the maximum propagation delay across the entire device. This ensures that even remote sequential elements receive the reset signal sufficiently before clock operation resumes, eliminating the need for complex delay compensation circuits while maintaining propagation consistency.
4Adaptability or versatility
If multiple reset sources are combined for global chip reset, then comprehensive system reset is achieved, but some parts of the system remain in non-reset state causing potential corruption
Solution Approach 1:
The reset management unit provides universal reset distribution by receiving reset assertions from multiple sources and propagating them uniformly to all sequential elements regardless of their original reset sources. This multi-functional unit ensures complete system state consistency while maintaining the ability to accept various reset sources, preventing corruption in previously non-reset areas.
Data Source
AI summary
An on-board reset circuit for a system-on-chip (SOC) addresses the problem of meta-stability in flip-flops on asynchronous reset that arises when different power domains or reset domains receive resets from different sources. To ameliorate the problem, a reset signal is asserted and de-asserted while the clocks are gated. The clocks are re-instated for a minimum period of time following assertion (or de-assertion) so that logic having synchronous reset can also receive the reset.