Reset Control Circuitry Synchronizing Independent Signals
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Solution Overview
Problem
In data processing systems with multiple independent reset signals, such as system and diagnostic resets, there is a lack of synchronization, leading to potential errors when diagnostic functions start before the system is fully ready, particularly due to delays in system reset signals caused by conditions like a phase-locked loop not being locked.
Innovation Solution
A reset control circuitry that synchronizes two independent reset signals by delaying the deassertion of one reset signal based on the other, ensuring they are deasserted at the same time or later, thereby maintaining independence while achieving synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two independent reset signals are used to reset system logic and diagnostic logic separately, then the system can be monitored through application of a system reset, but the diagnostic reset may not be similarly delayed and diagnosis may start before the system is ready to operate
Solution Approach 1:
A reset controller is introduced as an intermediary component that receives both the system reset signal and diagnostic reset signal, and mediates their timing by delaying the diagnostic reset deassertion until after the system reset deassertion, ensuring system readiness before diagnostic functions start
Solution Approach 2:
The system reset deassertion is delayed as a preliminary action to ensure the system is fully ready before the diagnostic reset deassertion occurs, preventing premature activation of diagnostic functions
2Reliability
If the system reset is delayed by a reset controller in response to detection of the processing apparatus not being ready, then the system is prepared properly, but the diagnostic reset may not be similarly delayed and errors can occur
Solution Approach 1:
The reset controller acts as an intermediary that monitors system readiness conditions and mediates the timing between system reset and diagnostic reset signals, applying the same delay logic to both signals to maintain synchronization
Solution Approach 2:
The reset controller uses feedback from system readiness detection (such as PLL lock status) to dynamically adjust the timing of both reset signals, ensuring they are deasserted at appropriate moments based on actual system state
Data Source
AI summary
Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.