Reset Detection Circuit Using Flip-Flop Pattern Verification
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Solution Overview
Problem
Digital electronic circuits face attacks where the reset signal is prevented from being asserted, allowing unauthorized access to features by enabling unintended functionality due to flip flops powering up in an undetermined state, leading to a 50% chance of incorrect initialization.
Innovation Solution
A dedicated reset detection circuitry system that monitors the assertion of the reset signal and outputs a confirmatory signal, which can trigger a reset if not asserted, using a group of flip flops configured to output a predetermined pattern upon successful reset, and a comparator to verify this pattern, ensuring proper initialization and enabling automatic reset assertion if necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the reset pin is left unasserted during power-up, then the circuit avoids forced initialization and maintains potential feature accessibility, but flip flops enter an undetermined state creating a 50% probability of incorrect feature initialization and enabling unauthorized access
Solution Approach 1:
The system performs preliminary detection of the reset signal assertion status during power-up before allowing normal operation. The detection circuit checks whether the reset signal was properly asserted, and if not, automatically asserts it to ensure correct initialization of flip flops and features before the system becomes operational.
Solution Approach 2:
The detection circuit continuously monitors the reset signal assertion status and provides feedback to control logic. Based on this feedback, the system determines whether to assert the reset signal automatically, creating a closed-loop control mechanism that ensures proper initialization while responding to actual circuit conditions.
2Reliability
If the reset signal is automatically asserted through detection circuitry, then initialization reliability is improved and unauthorized feature enabling is prevented, but the system complexity increases due to additional detection and control components
Solution Approach 1:
The detection circuit is integrated with the existing reset logic and flip flop structures, merging multiple functions into a unified circuit block. The detection circuit shares resources with the reset assertion mechanism, reducing the need for completely separate components and minimizing overall circuit complexity.
Solution Approach 2:
The detection circuit automatically detects reset signal assertion status and triggers automatic reset assertion without requiring external intervention or complex control logic. The system serves itself by autonomously monitoring and correcting its own initialization state, eliminating the need for additional external control mechanisms.
3Object-affected harmful factors
If detection circuitry is implemented to verify reset assertion, then security against attacks is improved, but the manufacturing cost and circuit area increase
Solution Approach 1:
The detection function is segmented into discrete logic stages that can be implemented using standard cell library components. The circuit is divided into detection elements, comparison logic, and control elements, allowing efficient placement and routing that minimizes overall circuit area while maintaining security functionality.
Data Source
AI summary
There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.