Reset Domain Control via Delayed Warning Signals
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Solution Overview
Problem
Reset Domain Crossing (RDC) issues in System-on-Chip (SoC) devices lead to metastability and errors when a source register in one reset domain resets while a destination register in a separate domain continues operation, causing data loss or arbitrary data generation due to unsynchronized reset signals across clock domains.
Innovation Solution
An integrated-circuit device with a central reset controller that introduces a predetermined delay between the reset warning and reset signals, ensuring communication completion before resetting the source register, and includes blocking circuitry to prevent sampling during resets, thereby preventing metastability and bus faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an asynchronous reset signal is used to reset the first reset domain, then the reset response time is reduced, but metastability occurs in the destination register due to unsynchronized reset across clock domains
Solution Approach 1:
The patent applies preliminary action by introducing a reset warning signal that is generated before the actual reset signal. This warning signal is sent to the destination register to prepare it for the upcoming reset, allowing the destination register to complete its sampling operation before the source register is reset. This prevents metastability while maintaining the fast response time of asynchronous resets.
2Reliability
If a synchronous reset signal is used to reset the first reset domain, then metastability is prevented, but the reset time is increased and productivity is reduced
Solution Approach 1:
The patent uses preliminary action to send a reset warning signal before the actual reset occurs. This allows the destination register to complete its sampling operation in advance, enabling the use of faster asynchronous reset signals without causing metastability. The preliminary warning signal gives the destination register enough time to prepare, effectively eliminating the need for synchronous resetting.
Solution Approach 2:
The reset warning signal acts as an intermediary between the reset controller and the destination register. This intermediary signal coordinates the reset operation across different clock domains, allowing the source register to be reset asynchronously while the destination register is prepared in advance. This mediator enables fast reset response without sacrificing reliability.
3Adaptability or versatility
If reset domain crossing communication is enabled, then system functionality is improved, but bus transaction faults occur due to unsynchronized reset operations
Solution Approach 1:
The patent applies preliminary action by generating and sending a reset warning signal to the destination register before the actual reset occurs. This warning signal allows the destination register to complete its sampling operation and prepare for the upcoming reset. As a result, reset domain crossing communication can proceed normally without causing bus transaction faults, maintaining both versatility and reliability.
Data Source
AI summary
An integrated-circuit device comprises a resettable source register in a first reset domain. A destination circuit, outside the first reset domain, is arranged to sample an output of the resettable source register. A digital logic module causes a central reset controller to output a reset-warning signal in response to receiving a request to reset first reset domain, and to reset the first domain after a predetermined delay period from outputting the reset-warning signal.