Reset Domain Crossing Metastability Detection in Integrated Circuits
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Solution Overview
Problem
Current reset design verification techniques fail to comprehensively and precisely detect Reset Domain Crossing (RDC) Metastability failures in integrated circuits, leading to costly and time-consuming diagnosis and repair of defective chips.
Innovation Solution
A software tool employing Timed Boolean Analysis and path tracing to identify potential RDC Metastability failures in integrated circuit designs, allowing for the detection of truly problematic paths and reducing analysis complexity and noise, thereby enabling the manufacture of defect-free integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If comprehensive static analysis is applied to detect all potential RDC Metastability failures, then detection completeness is improved, but computation time and resources increase significantly
Solution Approach 1:
The analysis is divided into distinct phases: first identifying reset domain crossings, then filtering for metastability conditions, and finally tracing problematic paths. This segmentation allows the tool to process large designs systematically without overwhelming computational resources at any single stage.
Solution Approach 2:
The tool performs preliminary identification of reset domain crossings and metastability conditions before conducting full path tracing. By pre-filtering potential issues, the tool reduces the scope of subsequent detailed analysis, thereby reducing overall computation time while maintaining detection completeness.
2Measurement precision
If comprehensive path tracing is performed to identify all problematic paths, then detection precision is improved, but analysis complexity and noise increase
Solution Approach 1:
The tool extracts and focuses only on the specific subset of paths that are both reset-domain-crossing paths and metastability-prone paths. By taking out only the relevant problematic paths from the entire design, the tool achieves high detection precision while avoiding the complexity of analyzing all possible paths.
Solution Approach 2:
The analysis applies different levels of scrutiny to different parts of the design based on their risk characteristics. Reset domain crossing points and metastability-prone regions receive detailed local analysis, while other areas are processed more efficiently, reducing overall analysis complexity while maintaining precision where needed.
3Reliability
If verification techniques are applied to detect reset-related failures, then reliability is improved, but manufacturing cost increases due to design re-spins
Solution Approach 1:
The tool performs verification of reset schemes during the design phase, identifying potential failures before manufacturing. By detecting and allowing correction of reset-related issues in the design stage rather than after manufacturing, the tool improves reliability while avoiding the high costs associated with design re-spins and defective chip recalls.
Data Source
AI summary
Integrated circuit failures caused by metastability related to assertion of asynchronous resets frequently escape detection before fabrication, causing design respins and severe economic loss. The numerous reset signals, flip-flops and complex logical interactions inherent in an integrated circuit cause an analysis for reset-metastability failures to be extremely noisy, reporting an unmanageable number of false failures and making early removal of failures impractical. Said noisy reporting arises because many flip-flops where reset-metastability manifests do not necessarily cause overall failure. An effective analysis of reset-metastability failures must identify all potential failures, but also must only report true failure potential. The present invention maximizes noise reduction by applying special conditions to identify flip-flops manifesting reset-metastability without causing integrated circuit failure, which can thereby be deemed safe. By reporting only true failure potential, the present invention enables efficient, robust and error-free removal of reset-related failures from an integrated circuit prior to fabrication.