Reset Hold Circuit for Capacitive-Load Tolerant Reset Pins
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Solution Overview
Problem
Existing reset circuits in microcontrollers face challenges in making internal reset events visible externally due to constraints on maximum load capacitance on reset pins, leading to unstable reset line propagation and potential miscommunication of reset conditions to external systems.
Innovation Solution
A closed-loop control mechanism using a reset holder digital logic that independently manages the reset line driving capability, allowing flexible configuration of pin functionalities and controlling the duration of the reset pulse to ensure the reset line reaches the desired threshold value regardless of capacitive load, thereby eliminating constraints on maximum capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a temporization function is implemented to allow reset propagation towards external systems, then reset events can be propagated externally, but the maximum load capacitance on the reset pin is constrained
Solution Approach 1:
The patent implements a feedback mechanism where the reset holder circuit monitors the reset signal state and automatically maintains the reset condition until properly cleared. The circuit detects when the reset signal is active and holds this state, providing feedback control that eliminates the need for external capacitance timing, thereby resolving the contradiction between reliable reset propagation and capacitive load adaptability
Solution Approach 2:
The reset holder circuit acts as an intermediary between the internal reset signal and the external reset pin. This intermediate circuit stage decouples the internal reset generation from the external pin characteristics, allowing the internal logic to control reset propagation independently of external capacitive loads, thus resolving the contradiction
2Device complexity
If the reset pin is shared with GPIO functionality to optimize package pin count, then pin count is reduced, but reset functionality may be compromised
Solution Approach 1:
The patent implements multi-functionality by allowing the same pin to serve both as a general-purpose I/O pin and as a reset pin with dedicated holder circuitry. The reset holder circuit is integrated into the pin control logic, enabling the pin to automatically function as a reset pin when needed while maintaining GPIO capabilities otherwise, thus resolving the contradiction between pin count reduction and reset functionality reliability
Solution Approach 2:
The pin configuration is made dynamic through the reset holder circuit that can automatically switch the pin between GPIO mode and reset mode based on the reset signal state. This dynamic reconfiguration allows the same physical pin to serve different functions at different times, resolving the contradiction between shared pin usage and dedicated reset functionality
Data Source
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AI summary
A circuit (10) for use, for instance, in a set/reset pad of a microcontroller, comprises: - a first node (AV33M) configured to receive a reset signal (hold_rst), - a reset drive stage (104) driving a reset node (IOFT), the reset drive stage (104) coupled to the first node (AV33M) via a reset signal path (100, 102) to propagate the reset signal (hold_rst) to the reset drive stage (104), wherein the reset drive stage (104) is activated as a result of assertion of a reset actuation state of the reset signal (hold_rst), - a sensing node (120) coupled to the reset node (IOFT) via a signal sensing path (108, 110), the sensing node sensitive to a signal level (IOFT_filt) of the reset node (IOFT) reaching a reset threshold (108), - a reset signal hold circuit block (200) coupled to the first node (AV33M) and configured to receive (202) a reset command signal (internal_rst) and assert the reset actuation state of the reset signal (hold_rst) at the first node (AV33M) as a result of the reset command signal (internal_rst) received, wherein the reset signal hold circuit block (200) is coupled to the sensing node (120) and configured to de-assert the reset actuation state of the reset signal (hold_rst) at the first node (AV33M) as a result of the signal level at the reset node (IOFT) reaching he aforesaid reset threshold (108).