Display Substrate Line Layout for Under-Screen Sensor Stability

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Solution Overview

Problem

OLED display devices applied to under-screen sensor products face issues with transmittance that affect sensor functionality due to inadequate design of signal lines and connections, leading to poor transmittance and stability.

Innovation Solution

A display substrate design with optimized signal line arrangements and conductive connections, including a reset signal line and initialization signal line, where the orthographic projections of these lines and their connections are strategically positioned to minimize overlap and reduce the size of conductive connection portions, thereby enhancing transmittance and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Illumination intensity

If the signal lines and conductive connections are designed with conventional layouts, then the circuit connectivity is ensured, but the transmittance of the OLED display device deteriorates

Engineering Contradiction:
ImprovetransmittanceVSAvoidcircuit connectivity
Core Design Contradiction:
Illumination intensityVSReliability

Solution Approach 1:

The patent positions the orthographic projection of the first electrode between the orthographic projections of the reset signal line and initialization signal line, creating a layered spatial arrangement that reduces planar overlap while maintaining electrical connectivity through vertical stacking of conductive elements

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the signal transmission path into separate dedicated lines (reset signal line and initialization signal line) with spatially separated projections, segmenting the circuit layout to reduce interference and improve transmittance while maintaining functional connectivity

Inventive Principle:
Principle #1Segmentation

2Reliability

If the conductive connection portion is designed with sufficient size to ensure connectivity, then the electrical connection is reliable, but the layout complexity and parasitic capacitance increase

Engineering Contradiction:
Improveelectrical connectionVSAvoidlayout complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent optimizes the conductive connection portion by positioning it locally between specific signal lines with controlled projection overlap, creating a localized connection structure that minimizes parasitic capacitance while ensuring reliable electrical connectivity where needed

Inventive Principle:
Principle #3Local quality

3Productivity

If the orthographic projections of signal lines and electrodes overlap significantly, then the circuit density is improved, but the crosstalk and parasitic capacitance increase

Engineering Contradiction:
Improvecircuit densityVSAvoidcrosstalk
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent resolves crosstalk issues by transitioning from planar separation to three-dimensional spatial arrangement, where the first electrode's projection is positioned between signal line projections, allowing vertical stacking that maintains density while reducing lateral interference and parasitic capacitance

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12471461B2Display substrate including a reset signal line and an initialization signal line and display device having the same
Publication Date: 2025.11.11 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US12471461B2 patent drawing
  • US12471461B2 patent drawing
  • US12471461B2 patent drawing

AI summary

The present disclosure provides a display substrate, and a display device. The display substrate includes a base substrate and a plurality of sub-pixels arranged on the base substrate; the sub-pixels include: a reset signal line, at least a part of the reset signal line extending along a first direction; an initialization signal line, at least a part of the initialization signal line extending along the first direction; a first transistor, a gate electrode of the first transistor being coupled to the reset signal line, a first electrode of the first transistor being coupled to the initialization signal line, an orthographic projection of at least part of the first electrode of the first transistor on the base substrate being located between an orthographic projection of the reset signal line on the base substrate and an orthographic projection of the initialization signal line on the base substrate.