Reset Signal Isolation for USB and Memory Wakeup Circuits

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Solution Overview

Problem

Existing semiconductor operations face delays and data loss during low power mode transitions due to slow initialization processes of IP blocks, particularly in USB and memory controller subsystems, which can lead to increased latency and energy inefficiency.

Innovation Solution

A circuit device isolates the power-on-reset signal during low power mode for USB and memory controller subsystems, preventing unnecessary resets and maintaining configuration settings, thereby allowing rapid restoration upon wakeup.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If IP blocks are initialized during wakeup from low power mode, then data corruption is prevented, but latency increases to match device startup delay

Engineering Contradiction:

Improvedata integrityVSAvoidwakeup latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The system segments power domains into multiple independent domains, allowing selective power management. Critical IP blocks remain in active domains while non-critical blocks enter low power mode, enabling differentiated initialization strategies that prevent unnecessary resets and reduce wakeup latency

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by maintaining configuration data in retention memory before entering low power mode. During wakeup, this pre-preserved data is restored without requiring full initialization sequences, significantly reducing latency while ensuring data integrity

Inventive Principle:

Principle #10Preliminary action

2Loss of energy

If power is shut off to IP blocks during low power mode, then energy consumption is reduced, but configuration data is lost or corrupted

Engineering Contradiction:

Improvepower consumptionVSAvoidconfiguration data

Core Design Contradiction:

Loss of energyVSLoss of information

Solution Approach 1:

The system applies local quality by providing different power management characteristics to different IP blocks. Retention memory receives maintained power supply during low power mode to preserve data, while other blocks receive reduced power, achieving energy savings without data loss in critical components

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

Retention memory acts as an intermediary that bridges the gap between power reduction and data preservation. It temporarily holds configuration data during low power mode, allowing IP blocks to be powered down while preventing data corruption

Inventive Principle:

Principle #24Intermediary (Mediator)

3Stability of the object's composition

If full initialization is performed upon wakeup, then system stability is ensured, but productivity decreases due to extended startup time

Engineering Contradiction:

Improvesystem stabilityVSAvoidoperational readiness

Core Design Contradiction:

Stability of the object's compositionVSProductivity

Solution Approach 1:

The system applies partial action by performing only necessary initialization steps upon wakeup. Critical functions receive full initialization while non-critical functions restore from retained data, achieving adequate system stability with reduced initialization time and improved productivity

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS12493340B2Power-on-reset signal isolation during lower power mode

Publication Date: 2025.12.09 TEXAS INSTRUMENTS INC

AI summary

A circuit device is provided and includes a first power domain comprising a universal serial bus (USB) subsystem and/or a memory controller subsystem. The first power domain is configured to isolate the USB subsystem and/or the memory controller subsystem from a power-on-reset signal asserted during a low power mode.