Reset-Latch Comparator for Low-Power Timing Detection
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Solution Overview
Problem
The existing comparator designs, such as those described in Japanese Patent Laying-Open No. 2008-153866, face challenges in reducing power consumption when used in applications that require high accuracy for detecting timing changes in analog voltages, particularly in one-shot type comparators used in relaxation oscillators, where the frequency of the clock signal needs to be enhanced to repeat comparison operations in short periods.
Innovation Solution
A comparator circuit configuration that includes a differential amplifier circuit, a current source circuit, an output stage, a current conversion circuit, a minimum selector circuit, and a latch circuit, which operates by generating currents proportional to voltage differences and using a reset signal to execute a positive feedback latch operation, allowing the output voltage to change only when the input voltage intersects with the reference voltage, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency of the clock signal is enhanced to repeat the comparison operation in a short period for high accuracy timing detection, then the measurement precision is improved, but the power consumption increases
Solution Approach 1:
The latch circuit is reset periodically using a reset signal that changes from L level to H level, enabling the comparator to perform comparison operations only at specific periodic intervals rather than continuously. This allows high-accuracy timing detection to be achieved at required moments while reducing power consumption during non-comparison periods by minimizing current flow in the latch circuit and output stage.
2Measurement precision
If the comparator operates continuously to maintain high accuracy detection capability, then the measurement precision is improved, but the power consumption increases
Solution Approach 1:
The comparator circuit transitions between different operational states dynamically: during reset operation (H level), the latch circuit is held in a high-impedance state with minimal current consumption; during comparison operation (L level), the circuit is activated for accurate timing detection. This dynamic state switching allows the comparator to maintain detection accuracy when needed while minimizing power consumption during idle periods.
Data Source
AI summary
A differential amplifier circuit generates a first current and a second current having a current difference obtained by amplifying a voltage difference between an input voltage and a reference voltage. An output stage supplies current proportional to the first current to an output node. A current conversion circuit discharges current proportional to the second current from the output node. After connecting the output node to a ground node in response to a reset signal, a latch circuit disconnects the output node from the ground node after reset cancellation. Thereafter, when voltage at the output node rises from the ground voltage in a case where a level relationship between the input voltage and the reference voltage is reversed from a reset cancellation time point, the latch circuit fixes the voltage at the output node to a power supply voltage by a positive feedback latch operation.