Reset Pad Circuit Hardening Against Hacker-Induced Reset Failure
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Solution Overview
Problem
Reset pads in digital devices, such as microcontrollers and Systems-On-Chip, are vulnerable to hacker attacks, which can disrupt normal operations and compromise security measures by preventing the activation of reset procedures.
Innovation Solution
A digital device with a reset pad circuit that includes a reset request propagating portion, an internal reset activation gate, a memory element, and a reset forwarding gate, which ensures that a reset operation is initiated and maintained independently of the state of the reset pad circuit, and includes redundancy and state keeping elements to protect against metastability and attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the reset pad circuit is made accessible from the outside for normal reset operations, then the ease of operation is improved, but the device becomes vulnerable to hacker attacks compromising security
Solution Approach 1:
The patent introduces an intermediary protection circuit between the external reset pad and the internal reset logic. This protection circuit includes detection circuitry that monitors reset signals and intermediates between the external reset request and the internal reset activation, preventing direct hacker access while allowing legitimate reset operations to proceed normally.
Solution Approach 2:
The patent implements preliminary detection and validation of reset signals before they reach the critical reset logic. The protection circuit performs preliminary checks to verify the authenticity of reset requests, blocking potential hacker attacks in advance while allowing genuine reset operations to pass through unchanged.
2Reliability
If the reset pad circuit is damaged by hacker attack, then the security measures are compromised, but the device should still be able to activate reset procedures for safety
Solution Approach 1:
The patent implements local quality by creating separate, independent paths for reset signal generation. The internal reset logic is isolated from external damage, with dedicated protection circuitry localized around the critical reset activation points, ensuring that damage to the external reset pad does not propagate to the internal reset functionality.
Solution Approach 2:
The patent provides beforehand cushioning by implementing redundant reset pathways and protection circuitry that cushions against potential damage. If the external reset pad is damaged, the internal reset generation circuitry can still activate reset procedures through alternative paths, preventing total failure of the reset function.
3Reliability
If redundancy elements are added to protect against attacks and metastability, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the reset circuit into distinct functional segments: external reset pad, protection/detection circuitry, internal reset logic, and output distribution. This segmentation allows redundancy to be added in specific critical areas without replicating the entire reset circuit, thereby limiting the increase in overall device complexity while maintaining reliability.
Data Source
AI summary
A reset pad circuit has first and second inputs coupled, respectively, to a first reset access port receiving a first reset request and a second reset access port. The reset pad circuit generates a first reset state signal. An internal reset activation gate has inputs coupled to internal resources and an output that applies a reset request to the second reset access port. A memory element has first and second inputs coupled, respectively, to the output of the reset activation gate and the output of the reset pad circuit. The memory element generates a second reset state signal when receiving the reset request until receiving the first reset state signal. A reset forward gate coupled to outputs of the reset pad circuit and the memory element generates a system reset request in response to the first reset state signal or the second state signal.