Reset Signal Pulse Expansion for Stable Semiconductor Initialization
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Solution Overview
Problem
Conventional semiconductor reset signal generation circuits are prone to pulse width instability due to PVT variations, leading to erroneous operations and defective semiconductor apparatuses.
Innovation Solution
A reset signal generation apparatus that includes a reset signal generation unit and a reset signal expansion unit, enabling and disabling the reset signal based on a pulse width extension signal, ensuring a sufficient pulse width through a configuration involving a reset command combination unit, test reset pulse generation unit, reset input signal generation unit, and reset signal expansion unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple delay elements are used to generate reset signal, then the reset signal can be generated through sequential delay, but the pulse width becomes unstable due to PVT variation
Solution Approach 1:
The patent changes the approach from using multiple delay elements (time-based parameter) to using a single delay element combined with signal expansion (logical parameter). The reset signal is expanded using a NAND gate to extend its pulse width, making it less sensitive to PVT variations while maintaining reliability.
Solution Approach 2:
The patent segments the reset signal generation into two independent parts: a single delay element for timing control and a NAND gate for pulse width expansion. This segmentation allows each component to perform its function optimally without the cumulative effects of multiple delay elements.
2Manufacturing precision
If external voltage level and skew affect delay elements, then the pulse width of reset signal cannot be sufficiently ensured, but increasing delay elements to compensate increases complexity
Solution Approach 1:
The patent introduces a NAND gate as an intermediary component that takes the delayed reset signal and expands it to the required pulse width. This intermediary approach ensures precise pulse width control without requiring multiple delay elements to be precisely matched, thereby improving manufacturing precision while keeping the delay element configuration simple.
3Reliability
If reset signal pulse width is insufficient, then internal circuits cannot be properly initialized, but extending pulse width through more delay elements increases sensitivity to PVT variation
Solution Approach 1:
The patent uses the periodic nature of clock signals to generate the reset signal, ensuring that the initialization operation occurs at a stable reference point in the clock cycle. This periodic approach ensures reliable initialization while the NAND gate expansion maintains pulse width stability independent of delay element PVT variations.
Data Source
AI summary
A reset signal generation apparatus includes a reset signal generation unit and a reset signal expansion unit. The reset signal generation unit enables a reset signal and an enable signal in response to a reset input signal, and disables the reset signal in response to a pulse width extension signal. The reset signal expansion unit generates the pulse width extension signal that is enabled for a predetermined time, in response to the enable signal.