Reset Signal Circuit Switching Between Synchronous and Asynchronous Modes
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Solution Overview
Problem
Existing semiconductor devices face issues with data loss and improper initialization due to the generation of asynchronous reset signals during power supply voltage fluctuations, which can lead to abnormal operation and failure in initializing synchronous circuits.
Innovation Solution
A reset signal generation circuit that detects the operation state of synchronous circuits and generates either synchronous or asynchronous reset signals based on the system clock signal, ensuring proper initialization and data preservation by using an operation detection circuit, signal control circuit, oscillation stabilization control, and determination circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If an asynchronous reset signal is generated during operation, then the circuit can be initialized immediately, but data stored in the memory may be lost
Solution Approach 1:
The reset signal generation mode dynamically switches between asynchronous and synchronous based on the operation state of the internal circuit. When the circuit is abnormal, asynchronous reset is enabled for immediate initialization. When normal operation is detected, synchronous reset is used to preserve data. This dynamic adaptation resolves the contradiction between fast initialization and data preservation.
2Loss of information
If a synchronous reset signal is generated irrespective of operation state, then data is preserved, but the circuit may not be initialized when abnormal operation occurs
Solution Approach 1:
An operation detection circuit continuously monitors the operation state of the internal circuit and provides feedback to the reset signal generation circuit. Based on this feedback, the system determines whether to generate asynchronous or synchronous reset signals, ensuring reliable initialization when abnormal conditions are detected while preserving data during normal operation.
3Loss of information
If the reset circuit generates synchronous reset signal when system clock signal is generated, then data is maintained, but the entire semiconductor device may fail to be initialized when oscillation stoppage factor is present
Solution Approach 1:
The oscillation control circuit preliminarily detects the presence of oscillation stoppage factors before the reset signal is generated. When such factors are detected, the system prepares to generate an asynchronous reset signal in advance, ensuring that the entire semiconductor device can be properly initialized even when clock oscillation is compromised, while normally maintaining data through synchronous reset.
Data Source
AI summary
A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.