Reset Sequence Simulation Convergence Detection
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Solution Overview
Problem
Current simulation-based verification methods for metastability convergence in electronic design are inefficient, as they require simulating all cycles of a long input sequence trace, leading to prolonged simulation times and uncertainty in determining the minimum number of cycles needed for reset propagation, due to unreliable metastability coverage metrics and lack of convergence checking in existing tools.
Innovation Solution
A computer-implemented method and system for performing a reset sequence simulation that samples and detects stability during initial cycles, bypasses sampling during remaining cycles where stability is achieved, and applies a convergence detection algorithm to fast-forward the simulation to the next input configuration, reducing the overall simulation time by identifying convergence between input trace value changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the simulator simulates all cycles of the input sequence trace, then complete reset sequence verification is achieved, but simulation time becomes excessively long
Solution Approach 1:
The patent implements convergence detection that allows the simulator to skip ahead through cycles where the reset state is already established and stable. When convergence is detected at a sampling point, the simulator fast-forwards to the next input configuration change point, bypassing unnecessary intermediate cycles. This resolves the contradiction by maintaining verification completeness while dramatically reducing simulation time for stable reset sequences.
Solution Approach 2:
The patent performs preliminary sampling at strategically chosen points during the reset sequence to detect convergence early. By sampling at these preliminary points and detecting when the reset state has stabilized, the system can determine ahead of time when further simulation is unnecessary, thus avoiding the time penalty of simulating all cycles while ensuring verification completeness.
2Productivity
If users manually determine the number of cycles for reset propagation, then simulation can be optimized, but accuracy is reduced due to trial and error process
Solution Approach 1:
The patent implements an automated feedback mechanism through convergence detection that continuously monitors the reset state during simulation. The system samples the design state at various points, detects when convergence has occurred, and automatically adjusts the simulation accordingly. This eliminates the need for manual trial-and-error cycle counting while maintaining high precision, as the feedback loop objectively determines the exact point of convergence rather than relying on user estimation.
3Adaptability or versatility
If existing tools verify convergence with reset constraints, then convergence checking is enabled, but it does not work with user-specified input trace reset sequences
Solution Approach 1:
The patent creates a universal convergence detection mechanism that works with both conventional reset constraints and user-specified input trace reset sequences. The sampling and convergence detection framework is designed to be agnostic to the specific reset definition method, allowing it to function with any reset specification approach. This resolves the contradiction by making the tool versatile enough to handle multiple reset definition styles without increasing complexity.
Data Source
AI summary
The present disclosure relates to a computer-implemented method for performing a reset sequence simulation in an electronic design. The method may include receiving, using at least one processor, a sequence file including at least one reset, input and cycle value. The method may further include sampling during a first set of cycles set forth in the sequence file and detecting stability at a time point during a first set of cycles. The method may also include bypassing sampling during one or more remaining time points of the first set of cycles, sampling during a second set of cycles set forth in the sequence file and detecting stability at a time point during a second set of cycles.